I am back after a forced vacation (surgery) and last Thursday I
participated in a meeting of the J extension for RISC-V. The idea of
(hence the "J") and I hope will also be good for OpenSmalltalk.
The current focus of the group is a small, but important detail which
they call "atomic instruction fetch". RISC-V supports conherence between
data caches in a multicore system, but depends on software to avoid
problems with the instruction caches. So if two or more cores share a
single compiled code cache in main memory and one of them makes changes
to that cache (as a result of an inline cache miss, for example) then
another core might see the old version of the code, or (even worse) a
mix of the old and new versions.
There is a separate group working on debugging features for RISC-V and I
suggested that dealing with execution counters for adaptive compilation
might overlap with whatever they come up with.
So far I don't think this work will help OpenSmalltalk much, but I will
continue to keep track and if I am able to extract data about our VM
that might be interesting for that group I will pass it on to them.
Boris Shingarov is part of that group and wanted to talk to me at this
year's ESUG. It is very unlikely that I will be able to go, but if
anyone here will be there it would be nice to discuss what RISC-V and
our VM could benifit from each other.
My own project has gone in a different direction than I described in
March so I no longer have the same personal interest in the J extension,
but I still plan to help in any way I can.