VM Maker: VMMaker.oscog-cb.994.mcz

 
ClementBera uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-cb.994.mcz

==================== Summary ====================

Name: VMMaker.oscog-cb.994
Author: cb
Time: 19 December 2014, 11:31:13.63 am
UUID: 09c70d1c-d75e-4095-9205-dec6b5080db6
Ancestors: VMMaker.oscog-cb.993

Fixed bugs in inlined primitive (I mixed some registers).

Fixed bug with inlined primitive sub for cst - reg (inlined primitive code was doing reg - cst)

=============== Diff against VMMaker.oscog-cb.993 ===============

Item was changed:
  ----- Method: StackToRegisterMappingCogit>>genBinaryConstOpVarInlinePrimitive: (in category 'inline primitive generators') -----
  genBinaryConstOpVarInlinePrimitive: prim
  "Const op var version of binary inline primitives."
  "SistaV1: 248 11111000 iiiiiiii mjjjjjjj Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 means inlined primitive, no hard return after execution.
  See EncoderForSistaV1's class comment and StackInterpreter>>#binaryInlinePrimitive:"
  | ra val untaggedVal |
  (ra := backEnd availableRegisterOrNilFor: self liveRegisters) ifNil:
  [self ssAllocateRequiredReg:
  (ra := optStatus isReceiverResultRegLive
  ifTrue: [Arg0Reg]
  ifFalse: [ReceiverResultReg])].
  ra = ReceiverResultReg ifTrue:
  [optStatus isReceiverResultRegLive: false].
  self ssTop popToReg: ra.
  self ssPop: 1.
  val := self ssTop constant.
  self ssPop: 1.
  untaggedVal := val - objectMemory smallIntegerTag.
  prim caseOf: {
  "0 through 6, +, -, *, /, //, \\, quo:, SmallInteger op SmallInteger => SmallInteger, no overflow"
  [0] -> [self AddCq: untaggedVal R: ra].
+ [1] -> [self MoveCq: untaggedVal R: TempReg.
+ self SubR: ra R: TempReg ].
- [1] -> [self SubCq: untaggedVal R: ra].
  [2] -> [objectRepresentation genRemoveSmallIntegerTagsInScratchReg: ra.
  self MoveCq: (objectMemory integerValueOf: val) R: TempReg.
  self MulR: TempReg R: ra.
  objectRepresentation genAddSmallIntegerTagsTo: ra].
 
  "2016 through 2019, bitAnd:, bitOr:, bitXor, bitShift:, SmallInteger op SmallInteger => SmallInteger, no overflow"
 
  "2032 through 2037, >, <, >=, <=. =, ~=, SmallInteger op SmallInteger => Boolean (flags?? then in jump bytecodes if ssTop is a flags value, just generate the instruction!!!!)"
 
  "2064 through 2068, Pointer Object>>at:, Byte Object>>at:, Short16 Word Object>>at: LongWord32 Object>>at: Quad64Word Object>>at:. obj op 0-rel SmallInteger => oop"
+ [64] -> [self genConvertSmallIntegerToIntegerInReg: ra.
+ self MoveCq: val R: TempReg.
+ self MoveXwr: ra R: TempReg R: ra ].
+ [65] -> [self genConvertSmallIntegerToIntegerInReg: ra.
+ self MoveCq: val R: TempReg.
+ self MoveXbr: ra R: TempReg R: ra ]
- [64] -> [untaggedVal := untaggedVal >> 1.
- self MoveXwr: untaggedVal R: ra R: ra ].
- [65] -> [untaggedVal := untaggedVal >> 1.
- self MoveXbr: untaggedVal R: ra R: ra ]
  }
  otherwise: [^EncounteredUnknownBytecode].
  self ssPushRegister: ra.
  ^0!

Item was changed:
  ----- Method: StackToRegisterMappingCogit>>genBinaryVarOpConstInlinePrimitive: (in category 'inline primitive generators') -----
  genBinaryVarOpConstInlinePrimitive: prim
  "Var op const version of inline binary inline primitives."
  "SistaV1: 248 11111000 iiiiiiii mjjjjjjj Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 means inlined primitive, no hard return after execution.
  See EncoderForSistaV1's class comment and StackInterpreter>>#binaryInlinePrimitive:"
  | rr val untaggedVal |
  (rr := backEnd availableRegisterOrNilFor: self liveRegisters) ifNil:
  [self ssAllocateRequiredReg:
  (rr := optStatus isReceiverResultRegLive
  ifTrue: [Arg0Reg]
  ifFalse: [ReceiverResultReg])].
  rr = ReceiverResultReg ifTrue:
  [optStatus isReceiverResultRegLive: false].
  val := self ssTop constant.
  self ssPop: 1.
  self ssTop popToReg: rr.
  self ssPop: 1.
  untaggedVal := val - objectMemory smallIntegerTag.
  prim caseOf: {
  "0 through 6, +, -, *, /, //, \\, quo:, SmallInteger op SmallInteger => SmallInteger, no overflow"
  [0] -> [self AddCq: untaggedVal R: rr].
+ [1] -> [self SubCq: untaggedVal R: rr ].
- [1] -> [self SubCq: untaggedVal R: rr].
  [2] -> [self flag: 'could use MulCq:R'.
  objectRepresentation genShiftAwaySmallIntegerTagsInScratchReg: rr.
  self MoveCq: (objectMemory integerValueOf: val) R: TempReg.
  self MulR: TempReg R: rr.
  objectRepresentation genAddSmallIntegerTagsTo: rr].
 
  "2016 through 2019, bitAnd:, bitOr:, bitXor, bitShift:, SmallInteger op SmallInteger => SmallInteger, no overflow"
 
  "2032 through 2037, >, <, >=, <=. =, ~=, SmallInteger op SmallInteger => Boolean (flags?? then in jump bytecodes if ssTop is a flags value, just generate the instruction!!!!)"
 
  "2064 through 2068, Pointer Object>>at:, Byte Object>>at:, Short16 Word Object>>at: LongWord32 Object>>at: Quad64Word Object>>at:. obj op 0-rel SmallInteger => oop"
  [64] -> [self genConvertSmallIntegerToIntegerInReg: rr.
+ self MoveCq: val >> 1 R: TempReg.
+ self MoveXwr: TempReg R: rr R: rr ].
- self MoveXwr: rr R: val R: rr ].
  [65] -> [self genConvertSmallIntegerToIntegerInReg: rr.
+ self MoveCq: val >> 1 R: TempReg.
+ self MoveXbr: TempReg R: rr R: rr ]
- self MoveXbr: rr R: val R: rr ]
 
  }
  otherwise: [^EncounteredUnknownBytecode].
  self ssPushRegister: rr.
  ^0!

Item was changed:
  ----- Method: StackToRegisterMappingCogit>>genBinaryVarOpVarInlinePrimitive: (in category 'inline primitive generators') -----
  genBinaryVarOpVarInlinePrimitive: prim
  "Var op var version of binary inline primitives."
  "SistaV1: 248 11111000 iiiiiiii mjjjjjjj Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 means inlined primitive, no hard return after execution.
  See EncoderForSistaV1's class comment and StackInterpreter>>#binaryInlinePrimitive:"
  | ra rr |
  (rr := backEnd availableRegisterOrNilFor: self liveRegisters) ifNil:
  [self ssAllocateRequiredReg:
  (rr := optStatus isReceiverResultRegLive
  ifTrue: [Arg0Reg]
  ifFalse: [ReceiverResultReg])].
  (ra := backEnd availableRegisterOrNilFor: (self liveRegisters bitOr: (self registerMaskFor: rr))) ifNil:
  [self ssAllocateRequiredReg: (ra := Arg1Reg)].
  (rr = ReceiverResultReg or: [ra = ReceiverResultReg]) ifTrue:
  [optStatus isReceiverResultRegLive: false].
  self ssTop popToReg: ra.
  self ssPop: 1.
  self ssTop popToReg: rr.
  self ssPop: 1.
  prim caseOf: {
  "0 through 6, +, -, *, /, //, \\, quo:, SmallInteger op SmallInteger => SmallInteger, no overflow"
  [0] -> [objectRepresentation genRemoveSmallIntegerTagsInScratchReg: ra.
  self AddR: ra R: rr].
  [1] -> [self SubR: ra R: rr.
  objectRepresentation genAddSmallIntegerTagsTo: rr].
  [2] -> [objectRepresentation genRemoveSmallIntegerTagsInScratchReg: rr.
  objectRepresentation genShiftAwaySmallIntegerTagsInScratchReg: ra.
  self MulR: ra R: rr.
  objectRepresentation genAddSmallIntegerTagsTo: rr].
 
  "2016 through 2019, bitAnd:, bitOr:, bitXor, bitShift:, SmallInteger op SmallInteger => SmallInteger, no overflow"
 
  "2032 through 2037, >, <, >=, <=. =, ~=, SmallInteger op SmallInteger => Boolean (flags?? then in jump bytecodes if ssTop is a flags value, just generate the instruction!!!!)"
 
  "2064 through 2068, Pointer Object>>at:, Byte Object>>at:, Short16 Word Object>>at: LongWord32 Object>>at: Quad64Word Object>>at:. obj op 0-rel SmallInteger => oop"
+ [64] -> [self genConvertSmallIntegerToIntegerInReg: ra.
+ self MoveXwr: ra R: rr R: rr ].
+ [65] -> [self genConvertSmallIntegerToIntegerInReg: ra.
+ self MoveXbr: ra R: rr R: rr ]
- [64] -> [self genConvertSmallIntegerToIntegerInReg: rr.
- self MoveXwr: rr R: ra R: ra ].
- [65] -> [self genConvertSmallIntegerToIntegerInReg: rr.
- self MoveXbr: rr R: ra R: ra ]
 
  }
  otherwise: [^EncounteredUnknownBytecode].
  self ssPushRegister: rr.
  ^0!