VM Maker: VMMaker.oscog-cb.995.mcz

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VM Maker: VMMaker.oscog-cb.995.mcz

commits-2
 
ClementBera uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-cb.995.mcz

==================== Summary ====================

Name: VMMaker.oscog-cb.995
Author: cb
Time: 19 December 2014, 11:39:18.871 am
UUID: 9e0e4367-220e-459a-807c-0878bfac2320
Ancestors: VMMaker.oscog-cb.994

Fixed a bug in inlined primitive sub (forgot to move to result register the result value).

Now that I understood that ra means registerArgument and rr registerReceiver, rewrote trinaryInlinePrimitive to use correct names.

=============== Diff against VMMaker.oscog-cb.994 ===============

Item was changed:
  ----- Method: StackToRegisterMappingCogit>>genBinaryConstOpVarInlinePrimitive: (in category 'inline primitive generators') -----
  genBinaryConstOpVarInlinePrimitive: prim
  "Const op var version of binary inline primitives."
  "SistaV1: 248 11111000 iiiiiiii mjjjjjjj Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 means inlined primitive, no hard return after execution.
  See EncoderForSistaV1's class comment and StackInterpreter>>#binaryInlinePrimitive:"
  | ra val untaggedVal |
  (ra := backEnd availableRegisterOrNilFor: self liveRegisters) ifNil:
  [self ssAllocateRequiredReg:
  (ra := optStatus isReceiverResultRegLive
  ifTrue: [Arg0Reg]
  ifFalse: [ReceiverResultReg])].
  ra = ReceiverResultReg ifTrue:
  [optStatus isReceiverResultRegLive: false].
  self ssTop popToReg: ra.
  self ssPop: 1.
  val := self ssTop constant.
  self ssPop: 1.
  untaggedVal := val - objectMemory smallIntegerTag.
  prim caseOf: {
  "0 through 6, +, -, *, /, //, \\, quo:, SmallInteger op SmallInteger => SmallInteger, no overflow"
  [0] -> [self AddCq: untaggedVal R: ra].
  [1] -> [self MoveCq: untaggedVal R: TempReg.
+ self SubR: ra R: TempReg.
+ self MoveR: TempReg R: ra ].
- self SubR: ra R: TempReg ].
  [2] -> [objectRepresentation genRemoveSmallIntegerTagsInScratchReg: ra.
  self MoveCq: (objectMemory integerValueOf: val) R: TempReg.
  self MulR: TempReg R: ra.
  objectRepresentation genAddSmallIntegerTagsTo: ra].
 
  "2016 through 2019, bitAnd:, bitOr:, bitXor, bitShift:, SmallInteger op SmallInteger => SmallInteger, no overflow"
 
  "2032 through 2037, >, <, >=, <=. =, ~=, SmallInteger op SmallInteger => Boolean (flags?? then in jump bytecodes if ssTop is a flags value, just generate the instruction!!!!)"
 
  "2064 through 2068, Pointer Object>>at:, Byte Object>>at:, Short16 Word Object>>at: LongWord32 Object>>at: Quad64Word Object>>at:. obj op 0-rel SmallInteger => oop"
  [64] -> [self genConvertSmallIntegerToIntegerInReg: ra.
  self MoveCq: val R: TempReg.
  self MoveXwr: ra R: TempReg R: ra ].
  [65] -> [self genConvertSmallIntegerToIntegerInReg: ra.
  self MoveCq: val R: TempReg.
  self MoveXbr: ra R: TempReg R: ra ]
  }
  otherwise: [^EncounteredUnknownBytecode].
  self ssPushRegister: ra.
  ^0!

Item was changed:
  ----- Method: StackToRegisterMappingCogit>>genTrinaryInlinePrimitive: (in category 'inline primitive generators') -----
  genTrinaryInlinePrimitive: prim
  "Unary inline primitives."
  "SistaV1: 248 11111000 iiiiiiii mjjjjjjj Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 means inlined primitive, no hard return after execution.
  See EncoderForSistaV1's class comment and StackInterpreter>>#trinaryInlinePrimitive:"
 
  | ra rr |
  (rr := backEnd availableRegisterOrNilFor: self liveRegisters) ifNil:
  [self ssAllocateRequiredReg:
  (rr := optStatus isReceiverResultRegLive
  ifTrue: [Arg0Reg]
  ifFalse: [ReceiverResultReg])].
  (ra := backEnd availableRegisterOrNilFor: (self liveRegisters bitOr: (self registerMaskFor: rr))) ifNil:
  [self ssAllocateRequiredReg: (ra := Arg1Reg)].
  (rr = ReceiverResultReg or: [ra = ReceiverResultReg]) ifTrue:
  [optStatus isReceiverResultRegLive: false].
  self ssTop popToReg: TempReg.
  self ssPop: 1.
- self ssTop popToReg: rr.
- self ssPop: 1.
  self ssTop popToReg: ra.
  self ssPop: 1.
+ self ssTop popToReg: rr.
+ self ssPop: 1.
  self ssPushRegister: TempReg.
+ self genConvertSmallIntegerToIntegerInReg: ra.
- self genConvertSmallIntegerToIntegerInReg: rr.
  "Now: ra is the variable object, rr is long, TempReg holds the value to store."
  prim caseOf: {
  "0 - 1 pointerAt:put: and byteAt:Put:"
+ [0] -> [ self MoveR: TempReg Xwr: ra R: rr ].
- [0] -> [ self MoveR: TempReg Xwr: rr R: ra ].
  [1] -> [ self genConvertSmallIntegerToIntegerInReg: TempReg.
+ self MoveR: TempReg Xbr: ra R: rr ]
- self MoveR: TempReg Xbr: rr R: ra ]
  }
  otherwise: [^EncounteredUnknownBytecode].
-
  ^0!