VM Maker: VMMaker.oscog-rmacnak.1537.mcz

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VM Maker: VMMaker.oscog-rmacnak.1537.mcz

commits-2
 
Ryan Macnak uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-rmacnak.1537.mcz

==================== Summary ====================

Name: VMMaker.oscog-rmacnak.1537
Author: rmacnak
Time: 30 November 2015, 8:32:24.833 pm
UUID: 090316cc-9bb5-4d24-9597-c464661d9b48
Ancestors: VMMaker.oscog-eem.1536

MIPS: Get simulation past the first display update.

Remove Jump[No]Overflow in noteFollowingConditionalBranch: as a different check is needed for add/sub and mul.

Use the right destination for MulRR. Rename locals in concretization of binops to help clarify the pattern.

Add the short-immediate variants of the binops.

Disable disassembly prints on code patching.

=============== Diff against VMMaker.oscog-eem.1536 ===============

Item was changed:
  ----- Method: CogMIPSELCompiler class>>initialize (in category 'class initialization') -----
  initialize
  "CogRTLOpcodes initialize. CogMIPSELCompiler initialize"
 
  super initialize.
 
  ConcreteVarBaseReg := S6.
 
  Cmp := T0.
 
  Overflow := T0.
  OverflowTemp1 := T1.
  OverflowTemp2 := T2.
 
  "Can't use AT, Cmp or Overflow because we may need to preserve them for sequences like
  CmpCwR
  JumpZero
  JumpBelow"
+ BranchTemp := T3.
- BranchTemp := T1.
 
  "OABI position independent code expects T9 to have its entry point on entry?"
  self flag: #OABI.
  TargetReg := T9.
 
  "Specific instructions"
  self initializeSpecificOpcodes: #(
  MulRR
  DivRR
  MoveLowR
  MoveHighR
  AddCheckOverflowCqR
  AddCheckOverflowRR
  MulCheckOverflowRR
  SubCheckOverflowCqR
  SubCheckOverflowRR
  BrEqualRR
  BrNotEqualRR
  BrUnsignedLessRR
  BrUnsignedLessEqualRR
  BrUnsignedGreaterRR
  BrUnsignedGreaterEqualRR
  BrSignedLessRR
  BrSignedLessEqualRR
  BrSignedGreaterRR
  BrSignedGreaterEqualRR
  BrLongEqualRR
  BrLongNotEqualRR)
  in: thisContext method
 
  !

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeAddCheckOverflowCqR (in category 'generate machine code - concretize') -----
  concretizeAddCheckOverflowCqR
+ | destReg leftReg rightImm |
+ rightImm := operands at: 0.
+ destReg := leftReg := self concreteRegister: (operands at: 1).
- | value reg |
- value := operands at: 0.
- reg := self concreteRegister: (operands at: 1).
- self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: value)).
- self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: value)).
 
+ self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)).
+ self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)).
+
  "Save original LHS"
+ self machineCodeAt: 8 put: (self adduR: OverflowTemp1 R: leftReg R: ZR).
- self machineCodeAt: 8 put: (self adduR: OverflowTemp1 R: reg R: ZR).
 
  "The actual addition"
+ self machineCodeAt: 12 put: (self adduR: destReg R: leftReg R: AT).
- self machineCodeAt: 12 put: (self adduR: reg R: reg R: AT).
 
  "Set sign bit of OverflowTemp2 if sign of result differs from sign of RHS."
+ self machineCodeAt: 16 put: (self xorR: OverflowTemp2 R: destReg R: AT).
- self machineCodeAt: 16 put: (self xorR: OverflowTemp2 R: reg R: AT).
  "Set sign bit of OverflowTemp1 if sign of result differs from sign of LHS."
+ self machineCodeAt: 20 put: (self xorR: OverflowTemp1 R: destReg R: OverflowTemp1).
- self machineCodeAt: 20 put: (self xorR: OverflowTemp1 R: reg R: OverflowTemp1).
  "Set sign bit of Overflow if sign of result differs from both LHS and RHS, which indicates overflow."
  self machineCodeAt: 24 put: (self andR: Overflow R: OverflowTemp1 R: OverflowTemp2).
  ^machineCodeSize := 28!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeAddCheckOverflowRR (in category 'generate machine code - concretize') -----
  concretizeAddCheckOverflowRR
+ | destReg leftReg rightReg |
+ rightReg := self concreteRegister: (operands at: 0).
+ destReg := leftReg := self concreteRegister: (operands at: 1).
- | leftReg rightReg |
- leftReg := self concreteRegister: (operands at: 0).
- rightReg := self concreteRegister: (operands at: 1).
 
+ "Save original LHS"
+ self machineCodeAt: 0 put: (self adduR: OverflowTemp1 R: leftReg R: ZR).
- "Save original RHS"
- self machineCodeAt: 0 put: (self adduR: OverflowTemp1 R: rightReg R: ZR).
 
  "The actual addition"
+ self machineCodeAt: 4 put: (self adduR: destReg R: leftReg R: rightReg).
- self machineCodeAt: 4 put: (self adduR: rightReg R: leftReg R: rightReg).
 
  "Set sign bit of OverflowTemp2 if sign of result differs from sign of RHS."
+ self machineCodeAt: 8 put: (self xorR: OverflowTemp2 R: destReg R: rightReg).
- self machineCodeAt: 8 put: (self xorR: OverflowTemp2 R: rightReg R: leftReg).
  "Set sign bit of OverflowTemp1 if sign of result differs from sign of LHS."
+ self machineCodeAt: 12 put: (self xorR: OverflowTemp1 R: destReg R: OverflowTemp1).
- self machineCodeAt: 12 put: (self xorR: OverflowTemp1 R: rightReg R: OverflowTemp1).
  "Set sign bit of Overflow if sign of result differs from both LHS and RHS, which indicates overflow."
  self machineCodeAt: 16 put: (self andR: Overflow R: OverflowTemp1 R: OverflowTemp2).
  ^machineCodeSize := 20!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeAddCqR (in category 'generate machine code - concretize') -----
  concretizeAddCqR
+ | destReg leftReg rightImm |
+ rightImm := operands at: 0.
+ destReg := leftReg := self concreteRegister: (operands at: 1).
+
+ (rightImm between: -16r8000 and: 16r7FFF) ifFalse: [^self concretizeAddCwR].
+
+ self machineCodeAt: 0 put: (self addiuR: destReg R: leftReg C: rightImm).
+ ^machineCodeSize := 4!
- ^self concretizeAddCwR!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeAddCwR (in category 'generate machine code - concretize') -----
  concretizeAddCwR
+ | destReg leftReg rightImm |
+ rightImm := operands at: 0.
+ destReg := leftReg := self concreteRegister: (operands at: 1).
+ self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)).
+ self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)).
+ self machineCodeAt: 8 put: (self adduR: destReg R: leftReg R: AT).
- | val reg |
- val := operands at: 0.
- reg := self concreteRegister: (operands at: 1).
- self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: val)).
- self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: val)).
- self machineCodeAt: 8 put: (self adduR: reg R: reg R: AT).
  ^machineCodeSize := 12!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeAddRR (in category 'generate machine code - concretize') -----
  concretizeAddRR
+ | destReg leftReg rightReg |
+ rightReg := self concreteRegister: (operands at: 0).
+ destReg := leftReg := self concreteRegister: (operands at: 1).
+ self machineCodeAt: 0 put: (self adduR: destReg R: leftReg R: rightReg).
- | leftReg rightReg |
- leftReg := self concreteRegister: (operands at: 0).
- rightReg := self concreteRegister: (operands at: 1).
- self machineCodeAt: 0 put: (self adduR: rightReg R: leftReg R: rightReg).
  ^machineCodeSize := 4!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeAndCqR (in category 'generate machine code - concretize') -----
  concretizeAndCqR
+ | destReg leftReg rightImm |
+ rightImm := operands at: 0.
+ destReg := leftReg := self concreteRegister: (operands at: 1).
+
+ (rightImm between: -16r8000 and: 16r7FFF) ifFalse: [^self concretizeAndCwR].
+
+ self machineCodeAt: 0 put: (self andiR: destReg R: leftReg C: rightImm).
+ ^machineCodeSize := 4!
- ^self concretizeAndCwR!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeAndCwR (in category 'generate machine code - concretize') -----
  concretizeAndCwR
+ | destReg leftReg rightImm |
+ rightImm := operands at: 0.
+ destReg := leftReg := self concreteRegister: (operands at: 1).
+ self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)).
+ self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)).
+ self machineCodeAt: 8 put: (self andR: destReg R: leftReg R: AT).
- | value reg |
- value := operands at: 0.
- reg := self concreteRegister: (operands at: 1).
- self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: value)).
- self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: value)).
- self machineCodeAt: 8 put: (self andR: reg R: reg R: AT).
  ^machineCodeSize := 12!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeAndRR (in category 'generate machine code - concretize') -----
  concretizeAndRR
+ | destReg leftReg rightReg |
+ rightReg := self concreteRegister: (operands at: 0).
+ destReg := leftReg := self concreteRegister: (operands at: 1).
+ self machineCodeAt: 0 put: (self andR: destReg R: leftReg R: rightReg).
- | leftReg rightReg |
- leftReg := self concreteRegister: (operands at: 0).
- rightReg := self concreteRegister: (operands at: 1).
- self machineCodeAt: 0 put: (self andR: rightReg R: leftReg R: rightReg).
  ^machineCodeSize := 4!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeBrSignedGreaterEqualRR (in category 'generate machine code - concretize') -----
  concretizeBrSignedGreaterEqualRR
  | offset leftReg rightReg |
  offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
  leftReg := self concreteRegister: (operands at: 1).
  rightReg := self concreteRegister: (operands at: 2).
+ self assert: leftReg ~= BranchTemp.
+ self assert: rightReg ~= BranchTemp.
  self machineCodeAt: 0 put: (self sltR: BranchTemp R: leftReg R: rightReg).
  self machineCodeAt: 4 put: (self beqR: BranchTemp R: ZR offset: offset).
  self machineCodeAt: 8 put: (self nop). "Delay slot"
  ^machineCodeSize := 12!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeBrSignedGreaterRR (in category 'generate machine code - concretize') -----
  concretizeBrSignedGreaterRR
  | offset leftReg rightReg |
  offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
  leftReg := self concreteRegister: (operands at: 1).
  rightReg := self concreteRegister: (operands at: 2).
+ self assert: leftReg ~= BranchTemp.
+ self assert: rightReg ~= BranchTemp.
  self machineCodeAt: 0 put: (self sltR: BranchTemp R: rightReg R: leftReg).
  self machineCodeAt: 4 put: (self bneR: BranchTemp R: ZR offset: offset).
  self machineCodeAt: 8 put: (self nop). "Delay slot"
  ^machineCodeSize := 12!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeBrSignedLessEqualRR (in category 'generate machine code - concretize') -----
  concretizeBrSignedLessEqualRR
  | offset leftReg rightReg |
  offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
  leftReg := self concreteRegister: (operands at: 1).
  rightReg := self concreteRegister: (operands at: 2).
+ self assert: leftReg ~= BranchTemp.
+ self assert: rightReg ~= BranchTemp.
  self machineCodeAt: 0 put: (self sltR: BranchTemp R: rightReg R: leftReg).
  self machineCodeAt: 4 put: (self beqR: BranchTemp R: ZR offset: offset).
  self machineCodeAt: 8 put: (self nop). "Delay slot"
  ^machineCodeSize := 12!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeBrSignedLessRR (in category 'generate machine code - concretize') -----
  concretizeBrSignedLessRR
  | offset leftReg rightReg |
  offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
  leftReg := self concreteRegister: (operands at: 1).
  rightReg := self concreteRegister: (operands at: 2).
+ self assert: leftReg ~= BranchTemp.
+ self assert: rightReg ~= BranchTemp.
  self machineCodeAt: 0 put: (self sltR: BranchTemp R: leftReg R: rightReg).
  self machineCodeAt: 4 put: (self bneR: BranchTemp R: ZR offset: offset).
  self machineCodeAt: 8 put: (self nop). "Delay slot"
  ^machineCodeSize := 12!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeBrUnsignedGreaterEqualRR (in category 'generate machine code - concretize') -----
  concretizeBrUnsignedGreaterEqualRR
  | offset leftReg rightReg |
  offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
  leftReg := self concreteRegister: (operands at: 1).
  rightReg := self concreteRegister: (operands at: 2).
+ self assert: leftReg ~= BranchTemp.
+ self assert: rightReg ~= BranchTemp.
  self machineCodeAt: 0 put: (self sltuR: BranchTemp R: leftReg R: rightReg).
  self machineCodeAt: 4 put: (self beqR: BranchTemp R: ZR offset: offset).
  self machineCodeAt: 8 put: (self nop). "Delay slot"
  ^machineCodeSize := 12!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeBrUnsignedGreaterRR (in category 'generate machine code - concretize') -----
  concretizeBrUnsignedGreaterRR
  | offset leftReg rightReg |
  offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
  leftReg := self concreteRegister: (operands at: 1).
  rightReg := self concreteRegister: (operands at: 2).
+ self assert: leftReg ~= BranchTemp.
+ self assert: rightReg ~= BranchTemp.
  self machineCodeAt: 0 put: (self sltuR: BranchTemp R: rightReg R: leftReg).
  self machineCodeAt: 4 put: (self bneR: BranchTemp R: ZR offset: offset).
  self machineCodeAt: 8 put: (self nop). "Delay slot"
  ^machineCodeSize := 12!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeBrUnsignedLessEqualRR (in category 'generate machine code - concretize') -----
  concretizeBrUnsignedLessEqualRR
  | offset leftReg rightReg |
  offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
  leftReg := self concreteRegister: (operands at: 1).
  rightReg := self concreteRegister: (operands at: 2).
+ self assert: leftReg ~= BranchTemp.
+ self assert: rightReg ~= BranchTemp.
  self machineCodeAt: 0 put: (self sltuR: BranchTemp R: rightReg R: leftReg).
  self machineCodeAt: 4 put: (self beqR: BranchTemp R: ZR offset: offset).
  self machineCodeAt: 8 put: (self nop). "Delay slot"
  ^machineCodeSize := 12!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeBrUnsignedLessRR (in category 'generate machine code - concretize') -----
  concretizeBrUnsignedLessRR
  | offset leftReg rightReg |
  offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
  leftReg := self concreteRegister: (operands at: 1).
  rightReg := self concreteRegister: (operands at: 2).
+ self assert: leftReg ~= BranchTemp.
+ self assert: rightReg ~= BranchTemp.
  self machineCodeAt: 0 put: (self sltuR: BranchTemp R: leftReg R: rightReg).
  self machineCodeAt: 4 put: (self bneR: BranchTemp R: ZR offset: offset).
  self machineCodeAt: 8 put: (self nop). "Delay slot"
  ^machineCodeSize := 12!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeJumpNoOverflow (in category 'generate machine code - concretize') -----
  concretizeJumpNoOverflow
+ self unreachable. "Should have been rewritten by noteFollowingConditionalBranch:"
+ ^0!
- | offset |
- offset := self computeJumpTargetOffsetPlus: 4.
- self flag: #BranchRange.
- self machineCodeAt: 0 put: (self bgezR: Overflow offset: offset).
- self machineCodeAt: 4 put: self nop. "Delay slot"
- ^machineCodeSize := 8!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeJumpOverflow (in category 'generate machine code - concretize') -----
  concretizeJumpOverflow
+ self unreachable. "Should have been rewritten by noteFollowingConditionalBranch:"
+ ^0!
- | offset |
- offset := self computeJumpTargetOffsetPlus: 4.
- self flag: #BranchRange.
- self machineCodeAt: 0 put: (self bltzR: Overflow offset: offset).
- self machineCodeAt: 4 put: self nop. "Delay slot"
- ^machineCodeSize := 8!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeMulCheckOverflowRR (in category 'generate machine code - concretize') -----
  concretizeMulCheckOverflowRR
+ | destReg leftReg rightReg |
+ rightReg := self concreteRegister: (operands at: 0).
+ destReg := leftReg := self concreteRegister: (operands at: 1).
- | leftReg rightReg |
- leftReg := self concreteRegister: (operands at: 0).
- rightReg := self concreteRegister: (operands at: 1). "Also destReg."
 
  "Overflow occured if the sign bit of the low part is different from the high part."
  self machineCodeAt: 0 put: (self multR: leftReg R: rightReg).
+ self machineCodeAt: 4 put: (self mfloR: destReg).
+ self machineCodeAt: 8 put: (self sraR: OverflowTemp1 R: destReg C: 31).
- self machineCodeAt: 4 put: (self mfloR: rightReg).
- self machineCodeAt: 8 put: (self sraR: OverflowTemp1 R: rightReg C: 31).
  self machineCodeAt: 12 put: (self mfhiR: OverflowTemp2).
+ ^machineCodeSize := 16!
- "Overflow contains 0 on overflow, non-zero otherwise."
- self machineCodeAt: 16 put: (self subuR: Overflow R: OverflowTemp1 R: OverflowTemp2).
- ^machineCodeSize := 20!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeOrCqR (in category 'generate machine code - concretize') -----
  concretizeOrCqR
+ | destReg leftReg rightImm |
+ rightImm := operands at: 0.
+ destReg := leftReg := self concreteRegister: (operands at: 1).
+
+ (rightImm between: 0 and: 16rFFFF) ifFalse: [^self concretizeOrCwR].
+
+ self machineCodeAt: 0 put: (self oriR: destReg R: leftReg C: rightImm).
+ ^machineCodeSize := 4!
- ^self concretizeOrCwR!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeOrCwR (in category 'generate machine code - concretize') -----
  concretizeOrCwR
+ | destReg leftReg rightImm |
+ rightImm := operands at: 0.
+ destReg := leftReg := self concreteRegister: (operands at: 1).
+ self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)).
+ self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)).
+ self machineCodeAt: 8 put: (self orR: destReg R: leftReg R: AT).
- | value reg |
- value := operands at: 0.
- reg := self concreteRegister: (operands at: 1).
- self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: value)).
- self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: value)).
- self machineCodeAt: 8 put: (self orR: reg R: reg R: AT).
  ^machineCodeSize := 12!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeOrRR (in category 'generate machine code - concretize') -----
  concretizeOrRR
+ | destReg leftReg rightReg |
+ rightReg := self concreteRegister: (operands at: 0).
+ destReg := leftReg := self concreteRegister: (operands at: 1).
+ self machineCodeAt: 0 put: (self orR: destReg R: leftReg R: rightReg).
- | leftReg rightReg |
- leftReg := self concreteRegister: (operands at: 0).
- rightReg := self concreteRegister: (operands at: 1).
- self machineCodeAt: 0 put: (self orR: rightReg R: leftReg R: rightReg).
  ^machineCodeSize := 4!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeSubCheckOverflowCqR (in category 'generate machine code - concretize') -----
  concretizeSubCheckOverflowCqR
+ | destReg leftReg rightImm |
+ rightImm := operands at: 0.
+ destReg := leftReg := self concreteRegister: (operands at: 1).
- | value reg |
- value := operands at: 0.
- reg := self concreteRegister: (operands at: 1).
- self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: value)).
- self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: value)).
 
+ self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)).
+ self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)).
+
  "Save original LHS"
+ self machineCodeAt: 8 put: (self adduR: OverflowTemp1 R: leftReg R: ZR).
- self machineCodeAt: 8 put: (self adduR: OverflowTemp1 R: reg R: ZR).
 
  "The actual subtraction"
+ self machineCodeAt: 12 put: (self subuR: destReg R: leftReg R: AT).
- self machineCodeAt: 12 put: (self subuR: reg R: reg R: AT).
 
  "Set sign bit of OverflowTemp2 if sign of result differs from sign of RHS."
+ self machineCodeAt: 16 put: (self xorR: OverflowTemp2 R: destReg R: AT).
- self machineCodeAt: 16 put: (self xorR: OverflowTemp2 R: reg R: AT).
  "Set sign bit of OverflowTemp1 if sign of result differs from sign of LHS."
+ self machineCodeAt: 20 put: (self xorR: OverflowTemp1 R: destReg R: OverflowTemp1).
- self machineCodeAt: 20 put: (self xorR: OverflowTemp1 R: reg R: OverflowTemp1).
  "Set sign bit of Overflow if sign of result differs from both LHS and RHS, which indicates overflow."
  self machineCodeAt: 24 put: (self andR: Overflow R: OverflowTemp1 R: OverflowTemp2).
  ^machineCodeSize := 28!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeSubCheckOverflowRR (in category 'generate machine code - concretize') -----
  concretizeSubCheckOverflowRR
+ | destReg leftReg rightReg |
+ rightReg := self concreteRegister: (operands at: 0).
+ destReg := leftReg := self concreteRegister: (operands at: 1).
- | leftReg rightReg |
- leftReg := self concreteRegister: (operands at: 0).
- rightReg := self concreteRegister: (operands at: 1).
 
+ "Save original LHS"
+ self machineCodeAt: 0 put: (self adduR: OverflowTemp1 R: leftReg R: ZR).
- "Save original RHS"
- self machineCodeAt: 0 put: (self adduR: OverflowTemp1 R: rightReg R: ZR).
 
  "The actual subtraction"
+ self machineCodeAt: 4 put: (self subuR: destReg R: leftReg R: rightReg).
- self machineCodeAt: 4 put: (self subuR: rightReg R: leftReg R: rightReg).
 
  "Set sign bit of OverflowTemp2 if sign of result differs from sign of RHS."
+ self machineCodeAt: 8 put: (self xorR: OverflowTemp2 R: destReg R: rightReg).
- self machineCodeAt: 8 put: (self xorR: OverflowTemp2 R: rightReg R: leftReg).
  "Set sign bit of OverflowTemp1 if sign of result differs from sign of LHS."
+ self machineCodeAt: 12 put: (self xorR: OverflowTemp1 R: destReg R: OverflowTemp1).
- self machineCodeAt: 12 put: (self xorR: OverflowTemp1 R: rightReg R: OverflowTemp1).
  "Set sign bit of Overflow if sign of result differs from both LHS and RHS, which indicates overflow."
  self machineCodeAt: 16 put: (self andR: Overflow R: OverflowTemp1 R: OverflowTemp2).
  ^machineCodeSize := 20!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeSubCqR (in category 'generate machine code - concretize') -----
  concretizeSubCqR
+ | destReg leftReg rightImm |
+ rightImm := operands at: 0.
+ destReg := leftReg := self concreteRegister: (operands at: 1).
+
+ (rightImm negated between: -16r8000 and: 16r7FFF) ifFalse: [^self concretizeSubCwR].
+
+ self machineCodeAt: 0 put: (self addiuR: destReg R: leftReg C: rightImm negated).
+ ^machineCodeSize := 4!
- ^self concretizeSubCwR!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeSubCwR (in category 'generate machine code - concretize') -----
  concretizeSubCwR
+ | destReg leftReg rightImm |
+ rightImm := operands at: 0.
+ destReg := leftReg := self concreteRegister: (operands at: 1).
+ self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)).
+ self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)).
+ self machineCodeAt: 8 put: (self subuR: destReg R: leftReg R: AT).
- | value reg |
- value := operands at: 0.
- reg := self concreteRegister: (operands at: 1).
- self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: value)).
- self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: value)).
- self machineCodeAt: 8 put: (self subuR: reg R: reg R: AT).
  ^machineCodeSize := 12!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeSubRR (in category 'generate machine code - concretize') -----
  concretizeSubRR
+ | destReg leftReg rightReg |
- | leftReg rightReg |
  rightReg := self concreteRegister: (operands at: 0).
+ destReg := leftReg := self concreteRegister: (operands at: 1).
+ self machineCodeAt: 0 put: (self subuR: destReg R: leftReg R: rightReg).
- leftReg := self concreteRegister: (operands at: 1).
- self machineCodeAt: 0 put: (self subuR: leftReg R: leftReg R: rightReg).
  ^machineCodeSize := 4!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeTstCqR (in category 'generate machine code - concretize') -----
  concretizeTstCqR
+ | leftReg rightImm |
+ rightImm := operands at: 0.
+ leftReg := self concreteRegister: (operands at: 1).
+
+ (rightImm between: -16r8000 and: 16r7FFF) ifFalse: [^self concretizeTstCwR].
+
+ self machineCodeAt: 0 put: (self andiR: Cmp R: leftReg C: rightImm).
+ ^machineCodeSize := 4!
- ^self concretizeTstCwR!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeTstCwR (in category 'generate machine code - concretize') -----
  concretizeTstCwR
+ | leftReg rightImm |
+ rightImm := operands at: 0.
+ leftReg := self concreteRegister: (operands at: 1).
+ self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)).
+ self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)).
+ self machineCodeAt: 8 put: (self andR: Cmp R: leftReg R: AT).
- | val reg |
- val := operands at: 0.
- reg := self concreteRegister: (operands at: 1).
- self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: val)).
- self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: val)).
- self machineCodeAt: 8 put: (self andR: Cmp R: reg R: AT).
  ^machineCodeSize := 12!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeXorCwR (in category 'generate machine code - concretize') -----
  concretizeXorCwR
+ | destReg leftReg rightImm |
+ rightImm := operands at: 0.
+ destReg := leftReg := self concreteRegister: (operands at: 1).
+ self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)).
+ self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)).
+ self machineCodeAt: 8 put: (self xorR: destReg R: leftReg R: AT).
- | val reg |
- val := operands at: 0.
- reg := self concreteRegister: (operands at: 1).
- self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: val)).
- self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: val)).
- self machineCodeAt: 8 put: (self xorR: reg R: reg R: AT).
  ^machineCodeSize := 12!

Item was changed:
  ----- Method: CogMIPSELCompiler>>concretizeXorRR (in category 'generate machine code - concretize') -----
  concretizeXorRR
+ | destReg leftReg rightReg |
+ rightReg := self concreteRegister: (operands at: 0).
+ destReg := leftReg := self concreteRegister: (operands at: 1).
+ self machineCodeAt: 0 put: (self xorR: destReg R: leftReg R: rightReg).
- | leftReg rightReg |
- leftReg := self concreteRegister: (operands at: 0).
- rightReg := self concreteRegister: (operands at: 1).
- self machineCodeAt: 0 put: (self xorR: rightReg R: leftReg R: rightReg).
  ^machineCodeSize := 4!

Item was changed:
  ----- Method: CogMIPSELCompiler>>isCallPrecedingReturnPC: (in category 'testing') -----
  isCallPrecedingReturnPC: mcpc
+ "cogit disassembleFrom: mcpc - 8 to: mcpc."
- cogit disassembleFrom: mcpc - 8 to: mcpc.
 
  (self opcodeAtAddress: mcpc - 8) = JAL ifTrue: [^true].
 
  ((self opcodeAtAddress: mcpc - 8) = SPECIAL
  and: [(self opcodeAtAddress: mcpc - 8) = JALR]) ifTrue: [^true].
 
  ^false!

Item was changed:
  ----- Method: CogMIPSELCompiler>>jumpLongConditionalTargetBeforeFollowingAddress: (in category 'inline cacheing') -----
  jumpLongConditionalTargetBeforeFollowingAddress: mcpc
- Transcript nextPutAll: mcpc hex; cr.
  "mcpc - 16: beq/ne Cmp, ZR, +12
  mcpc - 12: nop (delay slot)
  mcpc - 8: j psuedo-address
  mcpc - 4: nop (delay slot)"
  self assert: (((self opcodeAtAddress: mcpc - 16) == BEQ)
  or: [(self opcodeAtAddress: mcpc - 16) == BNE]).
  self assert: (objectMemory longAt: mcpc - 12) == self nop. "Delay slot"
  self assert: (self opcodeAtAddress: mcpc - 8) == J.
  self assert: (objectMemory longAt: mcpc - 4) == self nop. "Delay slot"
  ^self targetFromJTypeAtAddress: mcpc - 8!

Item was changed:
  ----- Method: CogMIPSELCompiler>>machineCodeWords (in category 'generate machine code') -----
  machineCodeWords
  "Answer the maximum number of words of machine code generated for any abstract instruction.
+ e.g. AddCheckOverflowCqR"
- e.g. CmpCwR =>
- lui at, <high>
- ori at, <low>
- subu Cmp, reg, at
- slt CmpSLT, reg, at
- slt CmpSGT, reg, at
- slt CmpULT, reg, at
- slt CmpUGT, reg, at"
- self flag: #inefficient.
  ^7!

Item was changed:
  ----- Method: CogMIPSELCompiler>>noteFollowingConditionalBranch: (in category 'abstract instructions') -----
  noteFollowingConditionalBranch: branch
  "Support for processors without condition codes, such as the MIPS.
  Answer the branch opcode.  Modify the receiver and the branch to
  implement a suitable conditional branch that doesn't depend on
  condition codes being set by the receiver."
  <var: #branch type: #'AbstractInstruction *'>
  | newBranchLeft newBranchOpcode newBranchRight |
+
+ ((branch opcode = JumpOverflow) or: [branch opcode = JumpNoOverflow])
+ ifTrue: [^self noteFollowingOverflowBranch: branch].
 
- ((branch opcode = JumpOverflow) or: [branch opcode = JumpNoOverflow]) ifTrue:
- [opcode := opcode caseOf: {
- [AddCqR] -> [AddCheckOverflowCqR].
- [AddRR] -> [AddCheckOverflowRR].
- [MulRR] -> [MulCheckOverflowRR].
- [SubCqR] -> [SubCheckOverflowCqR].
- [SubRR] -> [SubCheckOverflowRR].
- } otherwise: [self unreachable].
- ^branch].
-
  newBranchOpcode := branch opcode caseOf: {
  [JumpZero] -> [BrEqualRR].
  [JumpNonZero] -> [BrNotEqualRR].
  [JumpBelow] -> [BrUnsignedLessRR].
  [JumpBelowOrEqual] -> [BrUnsignedLessEqualRR].
  [JumpAbove] -> [BrUnsignedGreaterRR].
  [JumpAboveOrEqual] -> [BrUnsignedGreaterEqualRR].
  [JumpLess] -> [BrSignedLessRR].
  [JumpLessOrEqual] -> [BrSignedLessEqualRR].
  [JumpGreater] -> [BrSignedGreaterRR].
  [JumpGreaterOrEqual] -> [BrSignedGreaterEqualRR].
  [JumpLongZero] -> [BrLongEqualRR].
  [JumpLongNonZero] -> [BrLongNotEqualRR].
 
  [JumpNegative] -> [BrSignedLessRR].
  } otherwise: [self unreachable].
 
  opcode caseOf: {
  [BrEqualRR] -> ["I.e., two jumps after a compare."
  newBranchLeft := operands at: 1.
  newBranchRight := operands at: 2].
  [BrUnsignedLessRR] -> ["I.e., two jumps after a compare."
  newBranchLeft := operands at: 1.
  newBranchRight := operands at: 2].
 
  [CmpRR] -> [newBranchLeft := operands at: 1.
  newBranchRight := operands at: 0.
  opcode := Label].
  [CmpCqR] -> [newBranchLeft := operands at: 1.
  newBranchRight := AT.
  opcode := MoveCqR.
  operands at: 1 put: AT].
  [CmpCwR] -> [newBranchLeft := operands at: 1.
  newBranchRight := AT.
  opcode := MoveCwR.
  operands at: 1 put: AT].
  [TstCqR] -> [newBranchLeft := Cmp.
  newBranchRight := ZR].
  [AndCqR] -> [newBranchLeft := operands at: 1.
  newBranchRight := ZR].
  [AndCqRR] -> [newBranchLeft := operands at: 2.
  newBranchRight := ZR].
  [OrRR] -> [newBranchLeft := operands at: 1.
  newBranchRight := ZR].
  [XorRR] -> [newBranchLeft := operands at: 1.
  newBranchRight := ZR].
  [SubCwR] -> [newBranchLeft := operands at: 1.
  newBranchRight := ZR].
  [SubCqR] -> [newBranchLeft := operands at: 1.
  newBranchRight := ZR].
  [ArithmeticShiftRightCqR] -> [newBranchLeft := operands at: 1.
  newBranchRight := ZR].
  } otherwise: [self unreachable].
 
  branch rewriteOpcode: newBranchOpcode with: newBranchLeft with: newBranchRight.
  ^branch!

Item was added:
+ ----- Method: CogMIPSELCompiler>>noteFollowingOverflowBranch: (in category 'abstract instructions') -----
+ noteFollowingOverflowBranch: branch
+ "Support for processors without condition codes, such as the MIPS.
+ Answer the branch opcode.  Modify the receiver and the branch to
+ implement a suitable conditional branch that doesn't depend on
+ condition codes being set by the receiver."
+ <var: #branch type: #'AbstractInstruction *'>
+ | newBranchOpcode |
+
+ (opcode = MulRR) ifTrue:
+ [opcode := MulCheckOverflowRR.
+ newBranchOpcode := branch opcode caseOf: {
+ [JumpOverflow] -> [BrNotEqualRR].
+ [JumpNoOverflow] -> [BrEqualRR].
+ } otherwise: [self unreachable].
+ branch rewriteOpcode: newBranchOpcode with: OverflowTemp1 with: OverflowTemp2.
+ ^branch].
+
+
+ opcode := opcode caseOf: {
+ [AddCqR] -> [AddCheckOverflowCqR].
+ [AddRR] -> [AddCheckOverflowRR].
+ [SubCqR] -> [SubCheckOverflowCqR].
+ [SubRR] -> [SubCheckOverflowRR].
+ } otherwise: [self unreachable].
+
+ newBranchOpcode := branch opcode caseOf: {
+ [JumpOverflow] -> [BrSignedLessRR].
+ [JumpNoOverflow] -> [BrSignedGreaterEqualRR].
+ } otherwise: [self unreachable].
+ branch rewriteOpcode: newBranchOpcode with: Overflow with: ZR.
+ ^branch!

Item was changed:
  ----- Method: CogMIPSELCompiler>>relocateMethodReferenceBeforeAddress:by: (in category 'inline cacheing') -----
  relocateMethodReferenceBeforeAddress: pc by: delta
  | oldValue newValue |
+ "cogit disassembleFrom: pc - 8 to: pc."
- cogit disassembleFrom: pc - 8 to: pc.
 
  oldValue := self literalAtAddress: pc - 4.
  newValue := oldValue + delta.
  self literalAtAddress: pc - 4 put: newValue.
 
+ "cogit disassembleFrom: pc - 8 to: pc."
- cogit disassembleFrom: pc - 8 to: pc.
  self assert: (self literalAtAddress: pc - 4) = newValue.
  !

Item was changed:
  ----- Method: CogMIPSELCompiler>>rewriteCPICJumpAt:target: (in category 'inline cacheing') -----
  rewriteCPICJumpAt: addressFollowingJump target: jumpTargetAddress
  "Rewrite a jump instruction to call a different target.  This variant is used to reset the
  jumps in the prototype CPIC to suit each use,.  
  Answer the extent of the code change which is used to compute the range of the icache to flush."
  <var: #addressFollowingJump type: #usqInt>
  <var: #jumpTargetAddress type: #usqInt>
 
  "self CmpR: ClassReg R: TempReg.
  ^self JumpNonZero: 0"
 
  "bne s5, s3, +156 ; =BE7C
  nop (delay slot)
  .... <-- addressFollowingJump"
 
  self assert: (self opcodeAtAddress: addressFollowingJump - 8) = BNE.
  self assert: (objectMemory longAt: addressFollowingJump - 4) = self nop.
+ "cogit disassembleFrom: addressFollowingJump - 8 to: addressFollowingJump."
- cogit disassembleFrom: addressFollowingJump - 8 to: addressFollowingJump.
 
  self rewriteITypeBranchAtAddress: addressFollowingJump - 8 target: jumpTargetAddress.
 
  self assert: (self opcodeAtAddress: addressFollowingJump - 8) = BNE.
  self assert: (objectMemory longAt: addressFollowingJump - 4) = self nop.
+ "cogit disassembleFrom: addressFollowingJump - 8 to: addressFollowingJump."!
- cogit disassembleFrom: addressFollowingJump - 8 to: addressFollowingJump.!

Item was changed:
  ----- Method: CogMIPSELCompiler>>rewriteCallAt:target: (in category 'inline cacheing') -----
  rewriteCallAt: callSiteReturnAddress target: callTargetAddress
  "Rewrite a call instruction to call a different target.  This variant is used to link PICs
  in ceSendMiss et al,.  
  Answer the extent of the code change which is used to compute the range of the icache to flush."
  <var: #callSiteReturnAddress type: #usqInt>
  <var: #callTargetAddress type: #usqInt>
 
  "lui t9, stub/targetHigh
  ori t9, t9, stub/targetLow
  jalr t9
  nop (delay slot)
  ...  <-- callSiteReturnAddress"
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 16) = LUI.
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 12) = ORI.
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 8) = SPECIAL.
  self assert: (self functionAtAddress: callSiteReturnAddress - 8) = JALR.
  self assert: (objectMemory longAt: callSiteReturnAddress - 4) = self nop.
+ "cogit disassembleFrom: callSiteReturnAddress - 16 to: callSiteReturnAddress."
-
- cogit disassembleFrom: callSiteReturnAddress - 16 to: callSiteReturnAddress.
 
  self literalAtAddress: callSiteReturnAddress - 12 put: callTargetAddress.
 
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 16) = LUI.
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 12) = ORI.
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 8) = SPECIAL.
  self assert: (self functionAtAddress: callSiteReturnAddress - 8) = JALR.
  self assert: (objectMemory longAt: callSiteReturnAddress - 4) = self nop.
+ "cogit disassembleFrom: callSiteReturnAddress - 16 to: callSiteReturnAddress."
 
- cogit disassembleFrom: callSiteReturnAddress - 16 to: callSiteReturnAddress.
-
  ^20!

Item was changed:
  ----- Method: CogMIPSELCompiler>>rewriteConditionalJumpLongAt:target: (in category 'inline cacheing') -----
  rewriteConditionalJumpLongAt: callSiteReturnAddress target: callTargetAddress
  "Rewrite a jump instruction to call a different target.  This variant is used to reset the
  jumps in the prototype CPIC to suit each use,.  
  Answer the extent of the code change which is used to compute the range of the icache to flush."
  <var: #callSiteReturnAddress type: #usqInt>
  <var: #callTargetAddress type: #usqInt>
 
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 8) = J.
  self assert: (objectMemory longAt: callSiteReturnAddress - 4) = self nop.
+ "cogit disassembleFrom: callSiteReturnAddress - 8 to: callSiteReturnAddress."
- cogit disassembleFrom: callSiteReturnAddress - 8 to: callSiteReturnAddress.
 
  self rewriteJTypeAtAddress: callSiteReturnAddress - 8 target: callTargetAddress.
 
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 8) = J.
  self assert: (objectMemory longAt: callSiteReturnAddress - 4) = self nop.
+ "cogit disassembleFrom: callSiteReturnAddress - 8 to: callSiteReturnAddress."
- cogit disassembleFrom: callSiteReturnAddress - 8 to: callSiteReturnAddress.
  !

Item was changed:
  ----- Method: CogMIPSELCompiler>>rewriteInlineCacheAt:tag:target: (in category 'inline cacheing') -----
  rewriteInlineCacheAt: callSiteReturnAddress tag: cacheTag target: callTargetAddress
  "Rewrite an inline cache to call a different target for a new tag.  This variant is used
  to link unlinked sends in ceSend:to:numArgs: et al.  Answer the extent of the code
  change which is used to compute the range of the icache to flush."
 
  "MoveCwR ClassReg selectorIndex/expectedClass
  Call: unlinked send stub/expectedTarget
  Push ReceiverResult <-- callSiteReturnAddress"
 
  "lui s3, selector/tagHigh
  ori s3, s3, selector/tagLow
  lui t9, stub/targetHigh
  ori t9, t9, stub/targetLow
  jalr t9
  nop (delay slot)
  ...  <-- callSiteReturnAddress"
 
  <var: #callSiteReturnAddress type: #usqInt>
  <var: #callTargetAddress type: #usqInt>
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 24) = LUI.
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 20) = ORI.
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 16) = LUI.
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 12) = ORI.
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 8) = SPECIAL.
  self assert: (self functionAtAddress: callSiteReturnAddress - 8) = JALR.
  self assert: (objectMemory longAt: callSiteReturnAddress - 4) = self nop.
+ "cogit disassembleFrom: callSiteReturnAddress - 24 to: callSiteReturnAddress."
-
- cogit disassembleFrom: callSiteReturnAddress - 24 to: callSiteReturnAddress.
 
  self literalAtAddress: callSiteReturnAddress - 20 put: cacheTag.
  self literalAtAddress: callSiteReturnAddress - 12 put: callTargetAddress.
 
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 24) = LUI.
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 20) = ORI.
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 16) = LUI.
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 12) = ORI.
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 8) = SPECIAL.
  self assert: (self functionAtAddress: callSiteReturnAddress - 8) = JALR.
  self assert: (objectMemory longAt: callSiteReturnAddress - 4) = self nop.
+ "cogit disassembleFrom: callSiteReturnAddress - 24 to: callSiteReturnAddress."
 
- cogit disassembleFrom: callSiteReturnAddress - 24 to: callSiteReturnAddress.
-
  ^28!

Item was changed:
  ----- Method: CogMIPSELCompiler>>rewriteJumpLongAt:target: (in category 'inline cacheing') -----
  rewriteJumpLongAt: callSiteReturnAddress target: callTargetAddress
  "Rewrite a jump instruction to call a different target.  This variant is used to reset the
  jumps in the prototype CPIC to suit each use,.  
  Answer the extent of the code change which is used to compute the range of the icache to flush."
  <var: #callSiteReturnAddress type: #usqInt>
  <var: #callTargetAddress type: #usqInt>
 
  "lui t9, stub/targetHigh
  ori t9, t9, stub/targetLow
  jr t9
  nop (delay slot)
  ...  <-- callSiteReturnAddress"
 
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 16) = LUI.
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 12) = ORI.
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 8) = SPECIAL.
  self assert: (self functionAtAddress: callSiteReturnAddress - 8) = JR.
  self assert: (objectMemory longAt: callSiteReturnAddress - 4) = self nop.
+ "cogit disassembleFrom: callSiteReturnAddress - 16 to: callSiteReturnAddress."
-
- cogit disassembleFrom: callSiteReturnAddress - 16 to: callSiteReturnAddress.
 
  self literalAtAddress: callSiteReturnAddress - 12 put: callTargetAddress.
 
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 16) = LUI.
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 12) = ORI.
  self assert: (self opcodeAtAddress: callSiteReturnAddress - 8) = SPECIAL.
  self assert: (self functionAtAddress: callSiteReturnAddress - 8) = JR.
  self assert: (objectMemory longAt: callSiteReturnAddress - 4) = self nop.
+ "cogit disassembleFrom: callSiteReturnAddress - 16 to: callSiteReturnAddress."
 
- cogit disassembleFrom: callSiteReturnAddress - 16 to: callSiteReturnAddress.
-
  ^20!

Item was changed:
  ----- Method: CogMIPSELCompilerTests>>assertCheckQuickArithOpCodeSize: (in category 'as yet unclassified') -----
  assertCheckQuickArithOpCodeSize: bytes
+ self assert: bytes <= 12!
- self flag: #todo. "We always generate the full 3 instructions for now."
- self assert: bytes = 12!

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Re: VM Maker: VMMaker.oscog-rmacnak.1537.mcz

timrowledge


> On 01-12-2015, at 4:32 AM, [hidden email] wrote:
>
>
> Ryan Macnak uploaded a new version of VMMaker to project VM Maker:
> http://source.squeak.org/VMMaker/VMMaker.oscog-rmacnak.1537.mcz
>
> ==================== Summary ====================
>
> Name: VMMaker.oscog-rmacnak.1537
> Author: rmacnak
> Time: 30 November 2015, 8:32:24.833 pm
> UUID: 090316cc-9bb5-4d24-9597-c464661d9b48
> Ancestors: VMMaker.oscog-eem.1536
>
> MIPS: Get simulation past the first display update.

Congratulations That’s always a special moment.


tim
--
tim Rowledge; [hidden email]; http://www.rowledge.org/tim
Strange OpCodes: DO: Deadstart Operator