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[vwnc] x86 sarl curiosity...

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Eliot Miranda-2

[vwnc] x86 sarl curiosity...

Hi All,

anyone know the x86/IA32 really well? If so, read on. Otherwise save yourself the yawn.

I just tried to save an instruction in Cog;s generated bitShift: primitive. It seems to me that SARL (shift arithmetic right long) should set the sign flag based on the result, in fact it says as much in the manual; I quote from IA-32 Intel® Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z p 4-192

Flags Affected

The CF flag contains the value of the last bit shifted out of the destination operand; it is unde-

fined for SHL and SHR instructions where the count is greater than or equal to the size (in bits)

of the destination operand. The OF flag is affected only for 1-bit shifts (see "Description"

above); otherwise, it is undefined. The SF, ZF, and PF flags are set according to the result. If the

count is 0, the flags are not affected. For a non-zero count, the AF flag is undefined.

(my emphasis added). But neither the Bochs simulator nor my Intel Core Duo set the flags when doing sarl $1, %eax when %eax contains -1. Have I misread, or is the manual wrong?

TIA

Eliot

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Martin McClure-2

Re: [vwnc] x86 sarl curiosity...

Eliot Miranda wrote:

> Hi All,
>
> anyone know the x86/IA32 really well? If so, read on. Otherwise
> save yourself the yawn.
>
> I just tried to save an instruction in Cog;s generated bitShift:
> primitive. It seems to me that SARL (shift arithmetic right long)
> should set the sign flag based on the result, in fact it says as much in
> the manual; I quote from IA-32 Intel® Architecture Software
> Developer's Manual Volume 2B: Instruction Set Reference, N-Z p 4-192
>
> Flags Affected
>
> The CF flag contains the value of the last bit shifted out of the
> destination operand; it is unde-
>
> fined for SHL and SHR instructions where the count is greater than or
> equal to the size (in bits)
>
> of the destination operand. The OF flag is affected only for 1-bit
> shifts (see "Description"
>
> above); otherwise, it is undefined. The SF, ZF, and PF flags are set
> according to the result. If the
>
> count is 0, the flags are not affected. For a non-zero count, the AF
> flag is undefined.
>
>
> (my emphasis added). But neither the Bochs simulator nor my Intel Core
> Duo set the flags when doing sarl $1, %eax when %eax contains -1. Have
> I misread, or is the manual wrong?

Interesting. FWIW, the AMD64 arch manual (vol 3, p.220) also says that
an SAR will affect the SF flag.

Regards,

-Martin
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Eliot Miranda-2

Re: [vwnc] x86 sarl curiosity...

In reply to this post by Eliot Miranda-2

apologies; my bad. I'd used the wrong branch. jump greater (if 0 > v) is not the same as jump (if v) negative . I live and learn. Sorry for the noise.

On Wed, Jan 21, 2009 at 10:21 AM, Eliot Miranda <[hidden email]> wrote:

Hi All,

anyone know the x86/IA32 really well? If so, read on. Otherwise save yourself the yawn.

I just tried to save an instruction in Cog;s generated bitShift: primitive. It seems to me that SARL (shift arithmetic right long) should set the sign flag based on the result, in fact it says as much in the manual; I quote from IA-32 Intel® Architecture Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z p 4-192

Flags Affected

The CF flag contains the value of the last bit shifted out of the destination operand; it is unde-

fined for SHL and SHR instructions where the count is greater than or equal to the size (in bits)

of the destination operand. The OF flag is affected only for 1-bit shifts (see "Description"

above); otherwise, it is undefined. The SF, ZF, and PF flags are set according to the result. If the

count is 0, the flags are not affected. For a non-zero count, the AF flag is undefined.

(my emphasis added). But neither the Bochs simulator nor my Intel Core Duo set the flags when doing sarl $1, %eax when %eax contains -1. Have I misread, or is the manual wrong?

TIA

Eliot

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