Ooh, it would be awesome to run Squeak on this

Hi:

On 16 Apr 2013, at 18:28, Jeff Gonis <[hidden email]> wrote:

> Sounds like a job for RoarVM! I know that they prototyped it on a Tilera board, and this is probably very different, but it would at least give you a head start in utilising all of those cores.

The Epiphany architecture is at least from a high-level perspective very similar to Tilera's. On top of that, the tool chain for the Parallella is pretty much the standard you'd expect. So, it should be fairly simple to get the RoarVM running. Getting it up to speed is the hard part.

Best regards
Stefan

--
Stefan Marr
Software Languages Lab
Vrije Universiteit Brussel
Pleinlaan 2 / B-1050 Brussels / Belgium
http://soft.vub.ac.be/~smarr
Phone: +32 2 629 2974
Fax:   +32 2 629 3525

Colin Putney wrote:

> http://www.zdnet.com/parallella-the-99-linux-supercomputer-7000014036/

I bought one of those and plan to run Squeak on it when it arrives. But
as is, Squeak will only use one of the two ARM cores on the Xilinx Zynq
chip and will totally ignore the  16-core Epiphany Multicore Accelerator
chip (the article says 64 cores, but that would only have been the case
if the extended Kickstarter goal had been reached).

The advantage relative to the Broadcom chip in the Raspberry Pi is that
everything is documented and supported by open source software. So it
would be possible to patch Bitblt or FloatArray primitives, for example,
to use the accelerator.

Unfortunately, this isn't a $99 Tilera. So I don't think any of the
RoarVM work would apply to this board.

-- Jecel

Hi Jecel:

On 16 Apr 2013, at 18:54, "Jecel Assumpcao Jr." <[hidden email]> wrote:

> Unfortunately, this isn't a $99 Tilera. So I don't think any of the
> RoarVM work would apply to this board.

Why so pessimistic? 'any of the work'?

"All" it takes is to have a look at
http://www.adapteva.com/wp-content/uploads/2013/04/epiphany_sdk_reference.4.13.03.301.pdf

and implement

https://github.com/smarr/RoarVM/blob/master/vm/src/platform/ilib_os_interface.h
[..]/ilib_os_interface.cpp

as well as

[..]/ilib_message_queue.h
[..]/ilib_message_queue.cpp

I wouldn't call that impossible.
Section 12 and 13 of the manual look pretty much like what we would need.

As a short-cut, the posix variants of those platform files "should just work".
And, yes, I am talking about the 16 or 64 cores and not about the ARM part.



Best regards
Stefan

--
Stefan Marr
Software Languages Lab
Vrije Universiteit Brussel
Pleinlaan 2 / B-1050 Brussels / Belgium
http://soft.vub.ac.be/~smarr
Phone: +32 2 629 2974
Fax:   +32 2 629 3525

"What Adapteva has done is create a credit-card sized
parallel-processing board. This comes with a dual-core ARM A9
processor and a 64-core Epiphany Multicore Accelerator chip, along
with 1GB of RAM, a microSD card, two USB 2.0 ports, 10/100/1000
Ethernet, and an HDMI connection."

---

Sounds cool except for the 1GB.  Most any task needing, and able, to
leverage 64 cores wuould need way more than 1GB RAM.  Maybe
brute-force cipher attacks would be easier but with just 1GB can it be
used for good?

On Tue, Apr 16, 2013 at 11:21 AM, Colin Putney <[hidden email]> wrote:
> http://www.zdnet.com/parallella-the-99-linux-supercomputer-7000014036/
>
>
>

Stefan Marr wrote:
> As a short-cut, the posix variants of those platform files "should just work".
> And, yes, I am talking about the 16 or 64 cores and not about the ARM part.

That's great! I had thought that the 32KB per node local memory was too
small, but doing the math I see it is a total of 512KB for the 16 core
version which is not that much less than what the Tilera chips have.

By the way, I was just notified that the 64 core version was done after
all:

> http://www.kickstarter.com/projects/adapteva/parallella-a-supercomputer-for-everyone/posts

This has confused a lot of the Kickstarter backers.

Anyway, I did look at the documentation you mentioned as well as more
detailed information on the hardware that I hadn't seen yet. It still
isn't clear to me that it would just work, but I'll trust your judgement
on this over mine.

-- Jecel

Hi Jecel:

On 16 Apr 2013, at 23:51, "Jecel Assumpcao Jr." <[hidden email]> wrote:

> Stefan Marr wrote:
>> As a short-cut, the posix variants of those platform files "should just work".
>> And, yes, I am talking about the 16 or 64 cores and not about the ARM part.
>
> That's great! I had thought that the 32KB per node local memory was too
> small, but doing the math I see it is a total of 512KB for the 16 core
> version which is not that much less than what the Tilera chips have.

Ok, now I see. I reread the manuals and I was wrongly assuming that the rest of the 32-bit address space is actually mapped into the 1GB of memory. But that doesn't seem to be necessarily true. Can't really tell what they do. The different manuals are talking in very general terms about what could be.

So, the main difference between Tilera and Epiphany is cache-coherency. While that's a big selling point of the Tilera, Epiphany does seem to work entirely without caches. That means, the RoarVM would crawl pretty much. And indeed, it might already run out of memory while loading and distributing the image over the different cores.

So, saying 'it will work' is indeed overly optimistic. Even if it would get as far as executing a benchmark, that's pretty much what you could do with it.
In the worst case, you'd need to have the interpreter code and part of the image within those 32KB…

Best regards
Stefan



--
Stefan Marr
Software Languages Lab
Vrije Universiteit Brussel
Pleinlaan 2 / B-1050 Brussels / Belgium
http://soft.vub.ac.be/~smarr
Phone: +32 2 629 2974
Fax:   +32 2 629 3525