Branch: refs/heads/Cog
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https://github.com/OpenSmalltalk/opensmalltalk-vm Commit: 52d0b5d3b19974c3451d396aba88d33af3335f05
https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/52d0b5d3b19974c3451d396aba88d33af3335f05 Author: Eliot Miranda <
[hidden email]>
Date: 2021-01-18 (Mon, 18 Jan 2021)
Changed paths:
M nsspur64src/vm/cogit.h
M nsspur64src/vm/cogitARMv8.c
M nsspur64src/vm/cogitX64SysV.c
M nsspur64src/vm/cogitX64WIN64.c
M nsspur64src/vm/cointerp.c
M nsspur64src/vm/cointerp.h
M nsspur64src/vm/gcc3x-cointerp.c
M nsspursrc/vm/cogit.h
M nsspursrc/vm/cogitARMv5.c
M nsspursrc/vm/cogitIA32.c
M nsspursrc/vm/cogitMIPSEL.c
M nsspursrc/vm/cointerp.c
M nsspursrc/vm/cointerp.h
M nsspursrc/vm/gcc3x-cointerp.c
M spur64src/vm/cogit.h
M spur64src/vm/cogitARMv8.c
M spur64src/vm/cogitX64SysV.c
M spur64src/vm/cogitX64WIN64.c
M spur64src/vm/cointerp.c
M spur64src/vm/cointerp.h
M spur64src/vm/gcc3x-cointerp.c
M spursista64src/vm/cogit.h
M spursista64src/vm/cogitARMv8.c
M spursista64src/vm/cogitX64SysV.c
M spursista64src/vm/cogitX64WIN64.c
M spursista64src/vm/cointerp.c
M spursista64src/vm/cointerp.h
M spursista64src/vm/gcc3x-cointerp.c
M spursistasrc/vm/cogit.h
M spursistasrc/vm/cogitARMv5.c
M spursistasrc/vm/cogitIA32.c
M spursistasrc/vm/cogitMIPSEL.c
M spursistasrc/vm/cointerp.c
M spursistasrc/vm/cointerp.h
M spursistasrc/vm/gcc3x-cointerp.c
M spursrc/vm/cogit.h
M spursrc/vm/cogitARMv5.c
M spursrc/vm/cogitIA32.c
M spursrc/vm/cogitMIPSEL.c
M spursrc/vm/cointerp.c
M spursrc/vm/cointerp.h
M spursrc/vm/gcc3x-cointerp.c
M src/vm/cogit.h
M src/vm/cogitARMv5.c
M src/vm/cogitIA32.c
M src/vm/cogitMIPSEL.c
M src/vm/cointerp.c
M src/vm/cointerp.h
M src/vm/gcc3x-cointerp.c
Log Message:
-----------
CogVM source as per VMMaker.oscog-eem.2936
Cogit ARMv5 code generator: increase method alignment to allow the entry
alignment mask to be large enough, a la ARMv8. This is work in trying to
provide a V3 32-bit ARM JIT.