Branch: refs/heads/Cog Home: https://github.com/OpenSmalltalk/opensmalltalk-vm Commit: 7b54f324f15fa3092c0f6eac74ec58d978a2da85 https://github.com/OpenSmalltalk/opensmalltalk-vm/commit/7b54f324f15fa3092c0f6eac74ec58d978a2da85 Author: Eliot Miranda <[hidden email]> Date: 2019-11-18 (Mon, 18 Nov 2019) Changed paths: M build.linux32x86/gdbarm32/conf.COG M build.linux32x86/gdbarm32/makeem M build.linux64x64/gdbarm32/conf.COG M build.linux64x64/gdbarm32/makeem M build.macos32x86/gdbarm32/conf.COG M build.macos32x86/gdbarm32/makeem M build.macos64x64/gdbarm32/conf.COG M build.macos64x64/gdbarm32/makeem M platforms/iOS/plugins/GdbARMPlugin/Makefile M processors/ARM/exploration/Makefile M processors/ARM/exploration/Makefile64 M processors/ARM/exploration/printcpuctrl.c R processors/ARM/gdb-7.10/COPYING R processors/ARM/gdb-7.10/COPYING.LIB R processors/ARM/gdb-7.10/COPYING3 R processors/ARM/gdb-7.10/COPYING3.LIB R processors/ARM/gdb-7.10/ChangeLog R processors/ARM/gdb-7.10/MAINTAINERS R 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processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccflag_dr_imm3.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccflag_dr_imm3_uu.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccflag_pr_imm3.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccflag_pr_imm3_uu.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccflag_pr_pr.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccflag_pr_pr_uu.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccmv_cc_dr_dr.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccmv_cc_dr_pr.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccmv_cc_pr_pr.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccmv_ncc_dr_dr.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccmv_ncc_dr_pr.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_ccmv_ncc_pr_pr.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_comp3op_dr_and_dr.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_comp3op_dr_minus_dr.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_comp3op_dr_mix.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_comp3op_dr_or_dr.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_comp3op_dr_plus_dr.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_comp3op_dr_xor_dr.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_comp3op_pr_plus_pr_sh1.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_comp3op_pr_plus_pr_sh2.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_compi2opd_dr_add_i7_n.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_compi2opd_dr_add_i7_p.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_compi2opd_dr_eq_i7_n.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_compi2opd_dr_eq_i7_p.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_compi2opd_flags.S R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_compi2opd_flags_2.S R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_compi2opp_pr_add_i7_n.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_compi2opp_pr_add_i7_p.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_compi2opp_pr_eq_i7_n.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_compi2opp_pr_eq_i7_p.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dagmodik_lnz_imgebl.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dagmodik_lnz_imltbl.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dagmodik_lz_inc_dec.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dagmodim_lnz_imgebl.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dagmodim_lnz_imltbl.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dagmodim_lz_inc_dec.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_a0_pm_a1.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_a0a1s.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_a_abs_a.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_a_neg_a.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_aa_absabs.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_aa_negneg.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_abs.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_absabs.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_alhwx.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_awx.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_byteop1ew.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_byteop2.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_byteop3.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_bytepack.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_byteunpack.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_disalnexcpt.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_max.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_maxmax.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_min.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_minmin.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_mix.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_r_lh_a0pa1.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_r_negneg.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rh_m.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rh_p.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd12_m.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd12_p.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd20_m.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rh_rnd20_p.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rl_m.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rl_p.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd12_m.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd12_p.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd20_m.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rl_rnd20_p.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rlh_rnd.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rm.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rmm.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rmp.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rp.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rpm.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rpp.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rr_lph_a1a0.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rrpm.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rrpm_aa.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rrpmmp_sft_x.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_rrppmm_sft_x.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_saa.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_sat_aa.S R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_search.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32alu_sgn.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_a1a0.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_a1a0_iuw32.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_a1a0_m.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_i.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_ih.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_is.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_iu.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_m.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_s.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_t.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_tu.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a0_u.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_i.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_ih.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_is.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_iu.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_m.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_s.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_t.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_tu.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1_u.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_iutsh.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_m.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_mix.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_i.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_is.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_m.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_s.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a0_u.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_i.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_is.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_m.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_s.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1_u.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_i.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_is.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_m.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_s.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_a1a0_u.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mac_pair_mix.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_i.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_ih.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_is.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_iu.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_m.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_i.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_iutsh.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_s.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_t.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_m_u.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_mix.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_s.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_t.s R processors/ARM/gdb-7.10/sim/testsuite/sim/bfin/c_dsp32mult_dr_tu.s Log Message: ----------- Move the ARMv6/ARM32 processor simulator to the gdb-8.3.1-derviced code base. [ci skip] |
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