[OpenSmalltalk/opensmalltalk-vm] ᴀᴍᴅ⁶⁴ (long mode) : align branches within 32-Byte boundary (fix erratum skx102). (#506)

 

https://www.intel.com/content/www/us/en/processors/xeon/scalable/xeon-scalable-spec-update.html

The Decoded ICache caches decoded instructions, called micro‑ops (μops), coming out of the legacy decode pipeline. The next time the processor accesses the same code, the Decoded ICache provides the μops directly, speeding up program execution.
In some Intel® Processors, there’s an erratum (sk102) that may occur under complex microarchitectural conditions involving jump instructions that span across 64‑byte boundaries (cross cache lines).

Though not sure about other modes like protected mode which would means that if the ᴊɪᴛ is running on bare metal 32 bits ᴏꜱ (not in a ᴠᴍ) that the program would remain unaffected.

The aim is to mend the performance penalty on fixed ᴄᴘᴜs as well as prevent computers not running Linux that didn’t received a manufacturer’s ʙɪᴏꜱ update from crashing.
In that way, the ɢɴᴜ’s binutils are already patched. Other projects not related to smatalk are applying patches too.

—
You are receiving this because you are subscribed to this thread.
Reply to this email directly, view it on GitHub, or unsubscribe.

<script type="application/ld+json">[ { "@context": "http://schema.org", "@type": "EmailMessage", "potentialAction": { "@type": "ViewAction", "target": "https://github.com/OpenSmalltalk/opensmalltalk-vm/issues/506", "url": "https://github.com/OpenSmalltalk/opensmalltalk-vm/issues/506", "name": "View Issue" }, "description": "View this Issue on GitHub", "publisher": { "@type": "Organization", "name": "GitHub", "url": "https://github.com" } } ]</script>