Smalltalk › Squeak › Squeak - Dev

Squeak RISC-V ISA 32I Implementation

_‹ Previous Topic Next Topic _›

Classic

List

Threaded

5 messages Options

darth-cheney

Squeak RISC-V ISA 32I Implementation

Hi all,

I've hit a small milestone on a personal project that I would like to share. It is a Squeak implementation of the RISC-V ISA, along with a (very basic for now) CPU and memory for simulation and testing. You can find the project here.

So far I have only implemented the basic 32I instructions from the unprivileged ISA. My goal is to get the basic extension instructions implemented too, along with the 64I instructions. In terms of personal goals for the project, I'm thinking of doing something stupid like writing my own OS and Squeak seems like the kind of reduced-frustration environment that might curtail some of the inevitable hair-pulling.

Disclaimer: my knowledge of the low-level systems stuff is quite limited, so writing this package has been a learning experience. That's a polite way of saying "I have no idea what I'm actually doing." So if you spot any design choices you think are offensive or downright insane, please do file an issue or send me a message. I'm hoping that somehow this will be useful to the community.

If you'd like to give this a whirl, your best bet is to check out RVCPUBasic >> #bootstrap:, which takes an ordered collection of RVInstructions and loads them into the simulated memory starting at address 0. You can then send the #start message to the CPU and it will run through the instructions in memory one by one. For the moment there aren't any example "programs" to run here -- I'm open to suggestions!

I've tried to write tests as comprehensively as possible, but I'm sure I'm missing some important cases and there are certainly going to be bugs.

Shout out to the TwosComplement package, which really helped me figure things out when I was in a bind.

The repo is called "Safe Bet" because it's a "small(talk) risc"

Eric

Tony Garnock-Jones-5

Re: Squeak RISC-V ISA 32I Implementation

On 7/12/20 9:30 PM, Eric Gade wrote:
> I've hit a small milestone on a personal project that I would like to
> share. It is a Squeak implementation of the RISC-V ISA, along with a
> (very basic for now) CPU and memory for simulation and testing. You can
> find the project here <https://github.com/darth-cheney/safe-bet/>.

This looks like fun!

What kinds of applications or experiments do you have in mind for it?

> The repo is called "Safe Bet" because it's a "small(talk) risc"

Also, this is an excellent name :-)

Tony

Tobias Pape

Re: Squeak RISC-V ISA 32I Implementation

Hi!

> On 13.07.2020, at 09:01, Tony Garnock-Jones <[hidden email]> wrote:
>
> On 7/12/20 9:30 PM, Eric Gade wrote:
>> I've hit a small milestone on a personal project that I would like to
>> share. It is a Squeak implementation of the RISC-V ISA, along with a
>> (very basic for now) CPU and memory for simulation and testing. You can
>> find the project here <https://github.com/darth-cheney/safe-bet/>.
>
> This looks like fun!

I'm very happy about that.

>
> What kinds of applications or experiments do you have in mind for it?
>
>> The repo is called "Safe Bet" because it's a "small(talk) risc"
>
> Also, this is an excellent name :-)

very nice!

Jecel should have a look at that!

Best regards
-Tobias

darth-cheney

Re: Squeak RISC-V ISA 32I Implementation

On 13.07.2020, at 09:01, Tony Garnock-Jones <[hidden email]> wrote:

What kinds of applications or experiments do you have in mind for it?

My own ideas are not that well developed. Lately I've been particularly inspired by the Act 1 papers and would like to take a stab at making an "actor-based" system at the lowest levels -- ie, have the parts in hardware behave "as if" they were actors and then build a system on top of that. I have some early notions about how it would all come together, and I'm part of a new research group that might take up the question at some point, but it's early days yet and not our top priority.

I do think, however, that RISC-V could become the basis for new experiments that rethink a lot of computing truisms. One of the reasons I discovered Smalltalk in the first place is because I was asking myself why everything is Unix. Obviously I don't think it has to be.

But really I was hoping that smarter / more experienced people would come up with something, and I could just handle the grunt work!

Also, this is an excellent name :-)

Thanks!

On Mon, Jul 13, 2020 at 4:03 AM Tobias Pape <[hidden email]> wrote:

Jecel should have a look at that!

Jecel was kind enough to help me in the Squeak slack with some issues I was experiencing.

Eric

Jecel Assumpcao Jr

Re: Squeak RISC-V ISA 32I Implementation

Eric,

congratulations on your project!

An interesting direction to take this would be to make it compatible
with the processor simulator interface in Cog. In the case of ARM and
x86 this interface calls external programs but in the case of MIPS it is
a simulator written in Squeak. You can find this in the VMMaker package.
Something like this would be the first step in a port of OpenSmalltalk
VM to RISC-V.

-- Jecel