VM Maker: CogPools-ISAs-eem.4.mcz

 
Eliot Miranda uploaded a new version of CogPools-ISAs to project VM Maker:
http://source.squeak.org/VMMaker/CogPools-ISAs-eem.4.mcz

==================== Summary ====================

Name: CogPools-ISAs-eem.4
Author: eem
Time: 17 December 2019, 11:36:50.211284 am
UUID: 80ab019d-345a-4b35-a0f3-61869f0a2c98
Ancestors: CogPools-ISAs-eem.3

Add some instruction decode methods to ARMv8A64Opcodes (a work in progress!).

=============== Diff against CogPools-ISAs-eem.3 ===============

Item was added:
+ ----- Method: ARMv8A64Opcodes class>>extractOffsetFromBImm19: (in category 'accessing') -----
+ extractOffsetFromBImm19: word
+ self halt.
+ ^(word bitAnd: (1 bitShift: 25) - 1) - ((word bitAnd: (1 bitShift: 18)) bitShift: 2) bitShift: -5!

Item was added:
+ ----- Method: ARMv8A64Opcodes class>>extractOffsetFromBImm26: (in category 'accessing') -----
+ extractOffsetFromBImm26: word
+ ^(word bitAnd: (1 bitShift: 27) - 1) - ((word bitAnd: (1 bitShift: 25)) bitShift: 2)!

Item was added:
+ ----- Method: ARMv8A64Opcodes class>>extractOffsetFromLoadStore: (in category 'accessing') -----
+ extractOffsetFromLoadStore: word
+ "C4.1.4 Loads and Stores C4-266
+
+ Table C4-5 Encoding table for the Loads and Stores group
+
+ LDAPR/STLR (unscaled immediate) on page C4-279 signed imm9 12 - 20
+ Load/store register (unscaled immediate) on page C4-283 signed imm9 12 - 20
+ Load/store register (immediate post-indexed) on page C4-284 signed imm9 12 - 20
+ Load/store register (immediate pre-indexed) on page C4-286 signed imm9 12 - 20
+ Load/store register (pac) on page C4-297 signed imm9 12 - 20
+ Load/store register (unsigned immediate) on page C4-297 unsigned imm12 21 - 10"
+ ^(word >> 23 bitAnd: 2r001110110) = 2r001110010 "op0 = xx11, b27=1, b25=0, op2 = 1x"
+ ifTrue: [(word >> 10 bitAnd: 1 << 13 - 1) bitShift: word >> 30]
+ ifFalse: [self halt. (word >> 12 bitAnd: 1 << 10 - 1) - (word >> 10 bitAnd: 1 << 19)]!

Item was added:
+ ----- Method: ARMv8A64Opcodes class>>instructionIsAnyB: (in category 'testing') -----
+ instructionIsAnyB: word
+ "C4.1 A64 instruction set encoding on page C4-252"
+ | op0_101_op1MSB |
+ op0_101_op1MSB := word bitShift: -25.
+ ^op0_101_op1MSB = 2r0101010 "Conditional branch immediate"
+ or: [op0_101_op1MSB = 2r1101011 "Unconditional branch (register)"
+ or: [(op0_101_op1MSB bitAnd: 2r101010) = 2r0001010]] "Unconditional branch (immediate) & Compare/Test and branch (immediate)"!

Item was added:
+ ----- Method: ARMv8A64Opcodes class>>instructionIsAnyLoadStore: (in category 'testing') -----
+ instructionIsAnyLoadStore: word
+ "C4.1 A64 instruction set encoding on page C4-252"
+ ^((word bitShift: -25) bitAnd: 2r0101) = 2r0100!

Item was added:
+ ----- Method: ARMv8A64Opcodes class>>instructionIsB: (in category 'testing') -----
+ instructionIsB: anInteger
+ self shouldBeImplemented!

Item was added:
+ ----- Method: ARMv8A64Opcodes class>>instructionIsBImm19: (in category 'testing') -----
+ instructionIsBImm19: word
+ "C4.1.3 Branches, Exception Generating and System instructions C4-257"
+ | op0_101_op1MSB |
+ op0_101_op1MSB := word >> 24.
+ ^ op0_101_op1MSB = 2r0101010 "conditional branch immediate 19 23-5"
+ or: [op0_101_op1MSB = 2r0011010 "compare-and-branch immediate 19 23-5"
+ or: [op0_101_op1MSB = 2r1011010]] "compare-and-branch immediate 19 23-5"!

Item was added:
+ ----- Method: ARMv8A64Opcodes class>>instructionIsBImm26: (in category 'testing') -----
+ instructionIsBImm26: word
+ "Unconditional branch (immediate) C4-264"
+ ^(word >> 26 bitAnd: 2r11111) = 2r101!

Item was added:
+ ----- Method: ARMv8A64Opcodes class>>instructionIsPCRelativeLoad: (in category 'testing') -----
+ instructionIsPCRelativeLoad: word
+ "C4.1 A64 instruction set encoding on page C4-252
+ C4.1.4 Loads and Stores C4-266"
+ "op0,b27,b25,op2" "op0=xx01,b27=1,b25=0,op2=0x"
+ ^(word >> 23 bitAnd: 2r1110110) = 2r110000!