VM Maker: CogPools-ISAs-eem.5.mcz

 
Eliot Miranda uploaded a new version of CogPools-ISAs to project VM Maker:
http://source.squeak.org/VMMaker/CogPools-ISAs-eem.5.mcz

==================== Summary ====================

Name: CogPools-ISAs-eem.5
Author: eem
Time: 17 December 2019, 3:03:17.272586 pm
UUID: 2d8de1c4-e0b6-4350-905c-1bd18a2bac00
Ancestors: CogPools-ISAs-eem.4

ARMv8A64Opcodes: Fix some bit masks.
 Implement instructionIsAnyBX:.

=============== Diff against CogPools-ISAs-eem.4 ===============

Item was changed:
  ----- Method: ARMv8A64Opcodes class>>extractOffsetFromBImm19: (in category 'accessing') -----
  extractOffsetFromBImm19: word
  self halt.
+ ^(word bitAnd: (1 bitShift: 24) - 1) - ((word bitAnd: (1 bitShift: 23)) bitShift: 2) bitShift: -5!
- ^(word bitAnd: (1 bitShift: 25) - 1) - ((word bitAnd: (1 bitShift: 18)) bitShift: 2) bitShift: -5!

Item was changed:
  ----- Method: ARMv8A64Opcodes class>>extractOffsetFromBImm26: (in category 'accessing') -----
  extractOffsetFromBImm26: word
+ ^(word bitAnd: (1 bitShift: 26) - 1) - ((word bitAnd: (1 bitShift: 25)) bitShift: 1)!
- ^(word bitAnd: (1 bitShift: 27) - 1) - ((word bitAnd: (1 bitShift: 25)) bitShift: 2)!

Item was changed:
  ----- Method: ARMv8A64Opcodes class>>extractOffsetFromLoadStore: (in category 'accessing') -----
  extractOffsetFromLoadStore: word
  "C4.1.4 Loads and Stores C4-266
 
  Table C4-5 Encoding table for the Loads and Stores group
 
  LDAPR/STLR (unscaled immediate) on page C4-279 signed imm9 12 - 20
  Load/store register (unscaled immediate) on page C4-283 signed imm9 12 - 20
  Load/store register (immediate post-indexed) on page C4-284 signed imm9 12 - 20
  Load/store register (immediate pre-indexed) on page C4-286 signed imm9 12 - 20
  Load/store register (pac) on page C4-297 signed imm9 12 - 20
  Load/store register (unsigned immediate) on page C4-297 unsigned imm12 21 - 10"
  ^(word >> 23 bitAnd: 2r001110110) = 2r001110010 "op0 = xx11, b27=1, b25=0, op2 = 1x"
+ ifTrue: [(word >> 10 bitAnd: 1 << 12 - 1) bitShift: word >> 30]
+ ifFalse: [self halt. (word >> 12 bitAnd: 1 << 9 - 1) - (word >> 10 bitAnd: 1 << 19)]!
- ifTrue: [(word >> 10 bitAnd: 1 << 13 - 1) bitShift: word >> 30]
- ifFalse: [self halt. (word >> 12 bitAnd: 1 << 10 - 1) - (word >> 10 bitAnd: 1 << 19)]!

Item was changed:
  ----- Method: ARMv8A64Opcodes class>>instructionIsAnyB: (in category 'testing') -----
  instructionIsAnyB: word
+ "C4.1 A64 instruction set encoding on page C4-252
+ C4.1.3 Branches, Exception Generating and System instructions"
- "C4.1 A64 instruction set encoding on page C4-252"
  | op0_101_op1MSB |
  op0_101_op1MSB := word bitShift: -25.
  ^op0_101_op1MSB = 2r0101010 "Conditional branch immediate"
  or: [op0_101_op1MSB = 2r1101011 "Unconditional branch (register)"
  or: [(op0_101_op1MSB bitAnd: 2r101010) = 2r0001010]] "Unconditional branch (immediate) & Compare/Test and branch (immediate)"!

Item was added:
+ ----- Method: ARMv8A64Opcodes class>>instructionIsAnyBX: (in category 'testing') -----
+ instructionIsAnyBX: word
+ "C4.1 A64 instruction set encoding on page C4-252
+ C4.1.3 Branches, Exception Generating and System instructions"
+ | op0_101_op1MSB |
+ op0_101_op1MSB := word bitShift: -25.
+ ^op0_101_op1MSB = 2r1101011 "Unconditional branch (register) on page C4-262"!

Item was removed:
- ----- Method: ARMv8A64Opcodes class>>instructionIsB: (in category 'testing') -----
- instructionIsB: anInteger
- self shouldBeImplemented!