VM Maker: VMMaker.oscog-eem.2594.mcz

 
Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2594.mcz

==================== Summary ====================

Name: VMMaker.oscog-eem.2594
Author: eem
Time: 25 November 2019, 5:15:25.766951 pm
UUID: ed66c0f5-0e21-4a13-b5b7-6fd82c34c944
Ancestors: VMMaker.oscog-eem.2593

Progress towards ARMv8 code generation.  Add a BS version of computeMaximumSize.

=============== Diff against VMMaker.oscog-eem.2593 ===============

Item was changed:
  ----- Method: CogARMCompiler>>cResultRegister (in category 'abi') -----
  cResultRegister
+ "Answer the register through which C functions return integral results."
- "Answer the register through which C funcitons return integral results."
  <inline: true>
  ^R0!

Item was changed:
  CogAbstractInstruction subclass: #CogARMv8Compiler
  instanceVariableNames: ''
  classVariableNames: 'AL CC CS D0 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D2 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D3 D30 D31 D4 D5 D6 D7 D8 D9 EQ GE GT HI LE LS LT MI NE PL R0 R1 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R2 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R3 R30 R31 R4 R5 R6 R7 R8 R9 VC VS'
  poolDictionaries: 'ARMv8A64Opcodes'
  category: 'VMMaker-JIT'!
+
+ !CogARMv8Compiler commentStamp: 'eem 11/25/2019 16:30' prior: 0!
+ I generate ARMv8 machine code instructions from CogAbstractInstructions with CogRTLOpcodes.
+ Here in "Arm ARM" refers to
+ Arm® Architecture Reference Manual
+ Armv8, for Armv8-A architecture profile
+ https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile!

Item was added:
+ ----- Method: CogARMv8Compiler>>cResultRegister (in category 'abi') -----
+ cResultRegister
+ "Answer the register through which C functions return integral results."
+ <inline: true>
+ ^R0!

Item was added:
+ ----- Method: CogARMv8Compiler>>computeMaximumSize (in category 'generate machine code') -----
+ computeMaximumSize
+ "Because we don't use Thumb, each ARMv8 instruction has 4 bytes. Several
+ abstract opcodes need more than one instruction. Instructions that refer
+ to constants and/or literals depend on literals being stored in-line or out-of-line.
+
+ N.B.  The ^N forms are to get around the bytecode compiler's long branch
+ limits which are exceeded when each case jumps around the otherwise."
+
+ opcode
+ caseOf: {
+ "Noops & Pseudo Ops"
+ [Label] -> [^0].
+ [Literal] -> [^4].
+ [AlignmentNops] -> [^(operands at: 0) - 4].
+ [Fill32] -> [^4].
+ [Nop] -> [^4].
+ "Control"
+ [Call] -> [^4].
+ [CallFull] -> [^8].
+ [JumpR] -> [^4].
+ [Jump] -> [^4].
+ [JumpFull] -> [^8].
+ [JumpLong] -> [^4].
+ [JumpZero] -> [^4].
+ [JumpNonZero] -> [^4].
+ [JumpNegative] -> [^4].
+ [JumpNonNegative] -> [^4].
+ [JumpOverflow] -> [^4].
+ [JumpNoOverflow] -> [^4].
+ [JumpCarry] -> [^4].
+ [JumpNoCarry] -> [^4].
+ [JumpLess] -> [^4].
+ [JumpGreaterOrEqual] -> [^4].
+ [JumpGreater] -> [^4].
+ [JumpLessOrEqual] -> [^4].
+ [JumpBelow] -> [^4].
+ [JumpAboveOrEqual] -> [^4].
+ [JumpAbove] -> [^4].
+ [JumpBelowOrEqual] -> [^4].
+ [JumpLongZero] -> [^4].
+ [JumpLongNonZero] -> [^4].
+ [JumpFPEqual] -> [^8].
+ [JumpFPNotEqual] -> [^8].
+ [JumpFPLess] -> [^8].
+ [JumpFPGreaterOrEqual] -> [^8].
+ [JumpFPGreater] -> [^8].
+ [JumpFPLessOrEqual] -> [^8].
+ [JumpFPOrdered] -> [^8].
+ [JumpFPUnordered] -> [^8].
+ [RetN] -> [^(operands at: 0) = 0 ifTrue: [4] ifFalse: [8]].
+ [Stop] -> [^4].
+
+ "Arithmetic"
+ [AddCqR] -> [^8].
+ [AndCqR] -> [^8].
+ [AndCqRR] -> [^8].
+ [CmpCqR] -> [^8].
+ [OrCqR] -> [^8].
+ [SubCqR] -> [^8].
+ [TstCqR] -> [^8].
+ [XorCqR] -> [^8].
+ [AddCwR] -> [^8].
+ [AndCwR] -> [^8].
+ [CmpCwR] -> [^8].
+ [OrCwR] -> [^8].
+ [SubCwR] -> [^8].
+ [XorCwR] -> [^8].
+ [AddRR] -> [^4].
+ [AndRR] -> [^4].
+ [CmpRR] -> [^4].
+ [OrRR] -> [^4].
+ [XorRR] -> [^4].
+ [SubRR] -> [^4].
+ [NegateR] -> [^4].
+ [LoadEffectiveAddressMwrR] -> [8].
+
+ [LogicalShiftLeftCqR] -> [^4].
+ [LogicalShiftRightCqR] -> [^4].
+ [ArithmeticShiftRightCqR] -> [^4].
+ [LogicalShiftLeftRR] -> [^4].
+ [LogicalShiftRightRR] -> [^4].
+ [ArithmeticShiftRightRR] -> [^4].
+ [AddRdRd] -> [^4].
+ [CmpRdRd] -> [^4].
+ [SubRdRd] -> [^4].
+ [MulRdRd] -> [^4].
+ [DivRdRd] -> [^4].
+ [SqrtRd] -> [^4].
+ [ClzRR] -> [^4].
+ "Data Movement"
+ [MoveCqR] -> [^4].
+ [MoveCwR] -> [^4].
+ [MoveRR] -> [^4].
+ [MoveRdRd] -> [^4].
+ [MoveAwR] -> [^(self isAddressRelativeToVarBase: (operands at: 0))
+ ifTrue: [4]
+ ifFalse: [8]].
+ [MoveRAw] -> [^(self isAddressRelativeToVarBase: (operands at: 1))
+ ifTrue: [4]
+ ifFalse: [8]].
+ [MoveAbR] -> [^(self isAddressRelativeToVarBase: (operands at: 0))
+ ifTrue: [4]
+ ifFalse: [8]].
+ [MoveRAb] -> [^(self isAddressRelativeToVarBase: (operands at: 1))
+ ifTrue: [4]
+ ifFalse: [8]].
+ [MoveRMwr] -> [^self is12BitValue: (operands at: 1)
+ ifTrue: [:u :i| 4]
+ ifFalse: [8]].
+ [MoveRdM64r] -> [^8].
+ [MoveMbrR] -> [^self is12BitValue: (operands at: 0)
+ ifTrue: [:u :i| 4]
+ ifFalse: [8]].
+ [MoveRMbr] -> [^self is12BitValue: (operands at: 1)
+ ifTrue: [:u :i| 4]
+ ifFalse: [8]].
+ [MoveRM16r] -> [^self is12BitValue: (operands at: 1)
+ ifTrue: [:u :i| 4]
+ ifFalse: [8]].
+ [MoveM16rR] -> [self halt].
+ [MoveM64rRd] -> [^8].
+ [MoveMwrR] -> [^self is12BitValue: (operands at: 0)
+ ifTrue: [:u :i| 4]
+ ifFalse: [8]].
+ [MoveXbrRR] -> [^4].
+ [MoveRXbrR] -> [^4].
+ [MoveXwrRR] -> [^4].
+ [MoveRXwrR] -> [^4].
+ [PopR] -> [^4].
+ [PushR] -> [^4].
+ [PushCw] -> [self halt].
+ [PushCq] -> [self halt].
+ [PrefetchAw] -> [self halt].
+ "Conversion"
+ [ConvertRRd] -> [^8].
+ }.
+ ^0 "to keep C compiler quiet"
+ !

Item was added:
+ ----- Method: CogARMv8Compiler>>isPCDependent (in category 'testing') -----
+ isPCDependent
+ "Answer if the receiver is a pc-dependent instruction.  With out-of-line literals any instruction
+ that refers to a literal depends on the address of the literal, so add them in addition to the jumps."
+ ^self isJump
+  or: [opcode = AlignmentNops
+  or: [opcode ~= Literal and: [dependent notNil and: [dependent opcode = Literal]]]]!