VM Maker: VMMaker.oscog-eem.2606.mcz

 
Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2606.mcz

==================== Summary ====================

Name: VMMaker.oscog-eem.2606
Author: eem
Time: 8 December 2019, 2:38:42.049006 pm
UUID: a2ab4cbb-e163-42cc-acde-2d1766c6ab9f
Ancestors: VMMaker.oscog-eem.2605

A64 LogicalShiftLeftCqR, MoveAwR, SubCqR

=============== Diff against VMMaker.oscog-eem.2605 ===============

Item was added:
+ ----- Method: CogARMv8Compiler>>concretizeLogicalShiftLeftCqR (in category 'generate machine code - concretize') -----
+ concretizeLogicalShiftLeftCqR
+ "C6.2.17 ASR (immediate) C6-785 100100110 (1)
+ C6.2.177 LSL (immediate) C6-1075 110100110 (1)
+ C6.2.180 LSR (immediate) C6-1081 110100110 (1)"
+ | reg constant |
+ constant := operands at: 0.
+ reg := operands at: 1.
+ self assert: (constant between: 1 and: 63).
+ machineCode
+ at: 0
+ put: 2r1101001101 << 22
+ + (constant << 16)
+ + (63 << 10)
+ + (reg << 5)
+ + reg.
+ ^machineCodeSize := 4!

Item was added:
+ ----- Method: CogARMv8Compiler>>concretizeMoveAwR (in category 'generate machine code - concretize') -----
+ concretizeMoveAwR
+ "Will get inlined into concretizeAt: switch."
+ <inline: true>
+ | srcAddr destReg instrOffset|
+ srcAddr := operands at: 0.
+ destReg := operands at: 1.
+ "ldr srcReg, [VarBaseReg, #offset] except that this is illegal for SP/X31"
+ (self isAddressRelativeToVarBase: srcAddr) ifTrue:
+ [srcAddr < cogit varBaseAddress ifTrue:
+ [self shouldBeImplemented.
+ ^machineCodeSize := 4].
+ destReg ~= SP ifTrue:
+ [machineCode
+ at: 0
+ put: (self ldrn: VarBaseReg rt: destReg imm: srcAddr - cogit varBaseAddress shiftBy12: false).
+ ^machineCodeSize := 4].
+ machineCode
+ at: 0
+ put: (self ldrn: VarBaseReg rt: RISCTempReg imm: srcAddr - cogit varBaseAddress shiftBy12: false);
+ at: 1
+ put: (self movern: RISCTempReg rd: destReg).
+ ^machineCodeSize := 8].
+ "LEA ConcreteIPReg
+ ldr destReg, [ConcreteIPReg]"
+ instrOffset := self moveCw: srcAddr intoR: RISCTempReg.
+ self deny: SP = destReg.
+ machineCode
+ at: instrOffset // 4
+ put: (self ldrn: RISCTempReg rt: destReg imm: 0 shiftBy12: false).
+ ^machineCodeSize := instrOffset + 4!

Item was added:
+ ----- Method: CogARMv8Compiler>>concretizeSubCqR (in category 'generate machine code - concretize') -----
+ concretizeSubCqR
+ "Will get inlined into concretizeAt: switch."
+ <inline: true>
+ | constant reg offset |
+ constant := operands at: 0.
+ reg := operands at: 1.
+
+ self deny: reg = SP. "For now; how to add an immediate to the SP?"
+ self isPossiblyShiftableImm12: constant
+ ifTrue:
+ [:shift|
+ "C6.2.314 SUBS (immediate) C6-1321"
+ machineCode
+ at: 0
+ put: 2r111100010 << 23
+ + (shift ifTrue: [constant >> 2 + (1 << 22)] ifFalse: [constant << 10])
+ + (reg << 5)
+ + reg.
+ ^machineCodeSize := 4]
+ ifFalse: [].
+ offset := self moveCw: constant intoR: RISCTempReg.
+ "C6.2.313 SUBS (extended register) C6-1318"
+ machineCode
+ at: offset // 4
+ put: 2r11101011001
+ + (RISCTempReg << 16)
+ + (SXTX << 13)
+ + (reg << 5)
+ + reg.
+ ^machineCodeSize := offset + 4!