Nicolas Cellier uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-nice.2715.mcz==================== Summary ====================
Name: VMMaker.oscog-nice.2715
Author: nice
Time: 19 February 2020, 1:58:30.554369 am
UUID: 78e2f556-9829-42fe-963d-e19dfc43c0e9
Ancestors: VMMaker.oscog-nice.2714
Fix X64 register operand encoding when R8-R15 is used in LZCNT/BSR
The high bit of registers is encoded in rexw:r:x:b: R for reg/opcode (RO) and B for r/m (RM)
Currently, we do not use those registers with LZCNT/BSR, but let's not lay traps along the track.
=============== Diff against VMMaker.oscog-nice.2714 ===============
Item was changed:
----- Method: CogX64Compiler>>concretizeBSR (in category 'generate machine code - concretize') -----
concretizeBSR
"Bit Scan Reverse
First operand is input register (mask)
Second operand is output register (dest)"
"BSR"
<inline: true>
| dest maskReg |
maskReg := operands at: 0.
dest := operands at: 1.
- (dest <= 7 and: [maskReg <= 7])
- ifTrue: [machineCode at: 0 put: (self rexw: true r: 0 x: 0 b: 0)]
- ifFalse: ["Beware: operation is on 32bits for R8-15"machineCode at: 0 put: (self rexw: false r: 0 x: 0 b: 0)].
-
machineCode
+ at: 0 put: (self rexw: true r: dest x: 0 b: maskReg);
at: 1 put: 16r0F;
at: 2 put: 16rBD;
at: 3 put: (self mod: ModReg RM: maskReg RO: dest).
^4!
Item was changed:
----- Method: CogX64Compiler>>concretizeClzRR (in category 'generate machine code - concretize') -----
concretizeClzRR
"Count leading zeros
First operand is output (dest)
Second operand is input (mask)"
"LZCNT"
<inline: true>
| maskReg dest |
maskReg := operands at: 0.
dest := operands at: 1.
machineCode
at: 0 put: 16rF3;
+ at: 1 put: (self rexw: true r: dest x: 0 b: maskReg);
- at: 1 put: (self rexw: true r: 0 x: 0 b: 0);
at: 2 put: 16r0F;
at: 3 put: 16rBD;
at: 4 put: (self mod: ModReg RM: maskReg RO: dest).
^5!
Locked
