VM Maker: VMMaker.oscog-tpr.2591.mcz

 
tim Rowledge uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-tpr.2591.mcz

==================== Summary ====================

Name: VMMaker.oscog-tpr.2591
Author: tpr
Time: 24 November 2019, 11:43:59.349144 am
UUID: ff381407-add6-4400-9056-25ecc797f78e
Ancestors: VMMaker.oscog-eem.2590

Fill in some simple bits, extend comments to refer to ARM doc etc.
Add condition codes to class vars; maybe better in the opcodes pool?

=============== Diff against VMMaker.oscog-eem.2590 ===============

Item was changed:
  CogAbstractInstruction subclass: #CogARMv8Compiler
  instanceVariableNames: ''
+ classVariableNames: 'AL CC CS D0 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D2 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D3 D30 D31 D4 D5 D6 D7 D8 D9 EQ GE GT HI LE LS LT MI NE PL R0 R1 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R2 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R3 R30 R31 R4 R5 R6 R7 R8 R9 VC VS'
- classVariableNames: 'D0 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D2 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D3 D30 D31 D4 D5 D6 D7 D8 D9 R0 R1 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R2 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R3 R30 R31 R4 R5 R6 R7 R8 R9'
  poolDictionaries: 'ARMv8A64Opcodes'
  category: 'VMMaker-JIT'!

Item was added:
+ ----- Method: CogARMv8Compiler class>>ISA (in category 'translation') -----
+ ISA
+ "Answer the name of the ISA the receiver implements."
+ ^#ARMv8!

Item was added:
+ ----- Method: CogARMv8Compiler class>>identifyingPredefinedMacros (in category 'translation') -----
+ identifyingPredefinedMacros
+ "currently guesswork but we have to have something here"
+ ^#('__ARM_ARCH_8__'  '__arm__' '__arm64__' 'ARM64' )!

Item was changed:
  ----- Method: CogARMv8Compiler class>>initialize (in category 'class initialization') -----
  initialize
+ "Initialize various ARM64 instruction-related constants."
  "self initialize"
 
+ "main registers; a minor complication in reading the doc.
+ ARM refer to the 64bit registers as X0...30 and use R0...30 to refer to the 32bit lower halves.They also use a whole suite of names for the floating point/SIMD registers. See ARMARM DDI0487 B1.2.1 etc for the gory details.
+ Note that R30 (yes, yes, X30) is used as the link register and as such is not really a general purpose register.
+ Also note that R31 (named XZR in ARM doc) is a pseudo-register that always reads as 0 and writes to /dev/null.  
+ And note that unlike the ARM32, there is no general purpose register for either the PC or SP; a big difference. See ARMARM DDI0487 C1.2.5. wrt to both issues.
+
+ We will stick with R0...30 to refer to the 64 bit general regs and D0...31 (note the extra reg here!!) for the FP/SIMD regs"
  #( (D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31)
  (R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31)) do:
  [:classVarNames|
  classVarNames doWithIndex:
  [:k :v|
+ CogARMv8Compiler classPool at: k put: v - 1]].
+
+ "Condition Codes. Note that cc=16rF is mapped back to AL in AARCH64. Generally it shouldn't be used"
+ "Perhaps have these in the ARMv8A64Opcodes pool?"
+ EQ := 0.
+ NE := 1.
+ CS := 2.
+ CC := 3.
+ MI := 4.
+ PL := 5.
+ VS := 6.
+ VC := 7.
+ HI := 8.
+ LS := 9.
+ GE := 10.
+ LT := 11.
+ GT := 12.
+ LE := 13.
+ AL := 14.!
- CogARMv8Compiler classPool at: k put: v - 1]]!

Item was added:
+ ----- Method: CogARMv8Compiler class>>machineCodeDeclaration (in category 'translation') -----
+ machineCodeDeclaration
+ "Answer the declaration for the machineCode array.
+ AARCH64 instructions are 32-bits in length."
+ ^{#'unsigned int'. '[', self basicNew machineCodeWords printString, ']'}!

Item was added:
+ ----- Method: CogARMv8Compiler class>>wordSize (in category 'translation') -----
+ wordSize
+ "This is a 64-bit ISA"
+ ^8!

Item was added:
+ ----- Method: CogARMv8Compiler>>hasLinkRegister (in category 'testing') -----
+ hasLinkRegister
+ ^true "lr"!

Item was added:
+ ----- Method: CogARMv8Compiler>>hasThreeAddressArithmetic (in category 'testing') -----
+ hasThreeAddressArithmetic
+ "Answer if the receiver supports three-address arithmetic instructions (currently only AndCqRR)"
+ ^true!

Item was added:
+ ----- Method: CogARMv8Compiler>>isBigEndian (in category 'testing') -----
+ isBigEndian
+ ^false!

Item was added:
+ ----- Method: CogARMv8Compiler>>machineCodeAt: (in category 'accessing') -----
+ machineCodeAt: anOffset
+ "read aWord from machineCode, with little endian"
+ <inline: true>
+ ^machineCode at: anOffset // 4!

Item was added:
+ ----- Method: CogARMv8Compiler>>machineCodeAt:put: (in category 'accessing') -----
+ machineCodeAt: anOffset put: aWord
+ "add aWord to machineCode, with little endian"
+ <inline: true>
+ machineCode at: anOffset // 4 put: aWord!

Item was added:
+ ----- Method: CogARMv8Compiler>>machineCodeBytes (in category 'generate machine code') -----
+ machineCodeBytes
+ "Answer the maximum number of bytes of machine code generated for any abstract instruction.
+ e.g. CmpCwR =>
+ mov R3, #<addressByte1>, 12
+ orr R3, R3, #<addressByte2>, 8
+ orr R3, R3, #<addressByte3>, 4
+ orr R3, R3, #<addressByte4>, 0
+ cmp R?, R3
+ Likely to be quite different for AARCH64"
+ ^20!

Item was added:
+ ----- Method: CogARMv8Compiler>>machineCodeWords (in category 'generate machine code') -----
+ machineCodeWords
+ "Answer the maximum number of words of machine code generated for any abstract instruction.
+ e.g. CmpCwR =>
+ mov R3, #<addressByte1>, 12
+ orr R3, R3, #<addressByte2>, 8
+ orr R3, R3, #<addressByte3>, 4
+ orr R3, R3, #<addressByte4>, 0
+ cmp R?, R3
+ Likely to be quite different for AARCH64"
+ ^self machineCodeBytes// 4!

Item was changed:
  ----- Method: CogAbstractInstruction>>hasPCRegister (in category 'testing') -----
  hasPCRegister
+ "Answer if the processor has a generally addressable pc register, such as the ARM32.
- "Answer if the processor has a generally addressable pc register, such as the ARM.
  On such processors we can execute jumping to pop top of stack by popping into
+ the pc register.
+ Note that this is not a generic RISC feature.  The PowerPC does not
+ allow one to pop into the pc for example, and now the AARCH64 ARM works the same way.
+ So by default, answer false."
- the pc register.  Note that this is not a generic RISC feature.  The PowerPC does not
- allow one to pop into the pc for example.  So by default, answer false."
  ^false!