[squeak-dev] x86 sarl curiosity...

Eliot Miranda <eliot.miranda <at> gmail.com> writes:

>
>
> Hi All,
>
>     anyone know the x86/IA32 really well?  If so, read on.  Otherwise save
yourself the yawn.
>
> I just tried to save an instruction in Cog;s generated bitShift: primitive.
 It seems to me that SARL (shift arithmetic right long) should set the sign flag
based on the result, in fact it says as much in the manual; I quote from IA-32
Intel® Architecture Software Developer's Manual Volume 2B:  Instruction Set
Reference, N-Z p 4-192
>

Hi Eliot,
I guess you are adressing case of SmallInteger, otherwise I would understand
optimize as using some MMX 64 or 128 bits arithmetic (like PSRLLQ).
If relevant, check my trivial optimizations for large ints at
http://bugs.squeak.org/view.php?id=7109

Nicolas

Hi All,

    anyone know the x86/IA32 really well?  If so, read on.  Otherwise save yourself the yawn.

I just tried to save an instruction in Cog;s generated bitShift: primitive.  It seems to me that SARL (shift arithmetic right long) should set the sign flag based on the result, in fact it says as much in the manual; I quote from IA-32 Intel® Architecture Software Developer's Manual Volume 2B:  Instruction Set Reference, N-Z p 4-192

Flags Affected 

The CF flag contains the value of the last bit shifted out of the destination operand; it is unde- 

fined for SHL and SHR instructions where the count is greater than or equal to the size (in bits) 

of the destination operand. The OF flag is affected only for 1-bit shifts (see "Description" 

above); otherwise, it is undefined. The SF, ZF, and PF flags are set according to the result. If the 

count is 0, the flags are not affected. For a non-zero count, the AF flag is undefined.

(my emphasis added).  But neither the Bochs simulator nor my Intel Core Duo set the flags when doing sarl $1, %eax when %eax contains -1.  Have I misread, or is the manual wrong?

TIA

Eliot

Eliot - I know you've already moved past this problem, but in the future, gcc -S foo.c will create foo.s with the assembly generated by gcc.

David

On Jan 21, 2009, at 2:08 PM, Eliot Miranda wrote:

Hi Martin,  can you send me the assembly?  Or show me the opcodes? When I try this it doesn't work.  So I must be doing something differently.

and Hi!  Robert Hirschfeld mentioned you when he and I met last week.

On Wed, Jan 21, 2009 at 11:06 AM, Martin Beck <[hidden email]> wrote:

Hi Eliot,

Eliot Miranda wrote:
> Hi All,
>     anyone know the x86/IA32 really well?  If so, read on.  Otherwise save
> yourself the yawn.
>

[...]

> (my emphasis added).  But neither the Bochs simulator nor my Intel Core Duo
> set the flags when doing sarl $1, %eax when %eax contains -1.  Have I
> misread, or is the manual wrong?
>

I cannot confirm this. Using this simple C-Program:

int calc(int i) {
 return i >> 1;
}

int main() {
 printf("%i\n", calc(-1));
}

my GCC 4.3.2 generates a sarl %eax instruction as the assembler output
shows. Debugging it with Kdbg shows a change of the flags after the
instruction. In fact, CF and SF are set as (more or less) expected. I
also have a Intel Core 2 Duo.

Regards,
Martin